Datasheet AD8306 (Analog Devices) - 9

AD8306
voltage sensitivity. Most interfaces have additional small junc- handled using a supply of 4.5 V or greater. When using a fully- tion capacitances associated with them, due to active devices or balanced drive, the +3 dBV level may be achieved for the sup- ESD protection; these may be neither accurate nor stable. plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies Component numbering in each of these interface diagrams is in the range 10 MHz to 200 MHz these high drive levels are local. easily achieved using a matching network. Using such a net- work, having an inductor at the input, the input transient is
Enable Interface
eliminated. The chip-enable interface is shown in Figure 20. The current in R1 controls the turn-on and turn-off states of the band-gap
Limiter Output Interface
reference and the bias generator, and is a maximum of 100 µA The simplified limiter output stage is shown in Figure 22. The when Pin 8 is taken to 5 V. Left unconnected, or at any voltage bias for this stage is provided by a temperature-stable reference below 1 V, the AD8306 will be disabled, when it consumes a voltage of nominally 400 mV which is forced across the exter- sleep current of much less than 1 µA (leakage currents only); when nal resistor RLIM connected from Pin 9 (LMDR, or limiter tied to the supply, or any voltage above 2 V, it will be fully enabled. drive) by a special op amp buffer stage. The biasing scheme The internal bias circuitry requires approximately 300 ns for also introduces a slight “lift” to this voltage to compensate for either OFF or ON, while a delay of some 6 µs is required for the the finite current gain of the current source Q3 and the output supply current to fall below 10 µA. transistors Q1 and Q2. A maximum current of 10 mA is per- missible (RLIM = 40 Ω). In special applications, it may be desir-
ENBL
able to modulate the bias current; an example of this is provided
R1
in the Applications section. Note that while the bias currents are
60k
V
TO BIAS ENABLE
temperature stable, the ac gain of this stage will vary with tem-
1.3k
V perature, by –6 dB over a 120°C range. A pair of supply and temperature stable complementary cur- rents is generated at the differential output LMHI and LMLO
50k
V
4k
V (Pins 12 and 13), having a square wave form with rise and fall
COMM
times of typically 0.6 ns, when load resistors of 50 Ω are used. The voltage at these output pins may swing to 1.2 V below the supply voltage applied to VPS2 (Pin 15). Figure 20. Enable Interface Because of the very high gain bandwidth product of this ampli-
Input Interface
fier considerable care must be exercised in using the limiter Figure 21 shows the essentials of the signal input interface. The outputs. The minimum necessary bias current and voltage parasitic capacitances to ground are labeled CP; the differential swings should be used. These outputs are best utilized in a input capacitance, CD, mainly due to the diffusion capacitance fully-differential mode. A flux-coupled transformer, a balun, or of Q1 and Q2. In most applications both input pins are ac- an output matching network can be selected to transform these coupled. The switch S closes when Enable is asserted. When voltages to a single-sided form. Equal load resistors are recom- disabled, the inputs float, bias current IE is shut off, and the mended, even when only one output pin is used, and these coupling capacitors remain charged. If the log amp is disabled should always be returned to the same well decoupled node on for long periods, small leakage currents will discharge these the PC board. When the AD8306 is used only to generate an capacitors. If they are poorly matched, charging currents at RSSI output, the limiter should be completely disabled by power-up can generate a transient input voltage which may omitting R block the lower reaches of the dynamic range until it has be- LIM and strapping LMHI

and LMLO to VPS2. come much less than the signal.
VPS2 LMHI LMLO VPS1 1.3k
V
1.3k
V
TO STAGES S 1 THRU 5 1.78V 67
V
67
V
Q1 3.65k
V
3.65k
V
FROM FINAL 4e C I C INHI B = 15mA 1.725V Q1 TO 2ND LIMITER STAGE Q2 STAGE SIGNAL C 20e 4e R D INPUT IN = 1k
V
R 2.5pF IN = 3k
V
Q2 400mV 1.725V 20e C OA ZERO-TC C INLO 2.6k
V
Q3 GAIN BIAS 2.6k
V
1.3k
V
1.3k
V
(TOP-END 1.26V COM1 DETECTORS) CP CP 130
V
3.4mA PTAT LMDR COMM RLIM
Figure 21. Signal Input Interface Figure 22. Limiter Output Interface In most applications, the input signal will be single-sided, and
RSSI Output Interface
may be applied to either Pin 4 or 5, with the remaining pin ac- The outputs from the ten detectors are differential currents, coupled to ground. Under these conditions, the largest input having an average value that is dependent on the signal input signal that can be handled is –3 dBV (sine amplitude of 1 V) level, plus a fluctuation at twice the input frequency. The cur- when operating from a 3 V supply; a +3 dBV input may be rents are summed at the internal nodes LGP and LGN shown in Figure 23. A further current IT is added to LGP, to position –8– REV. A