Datasheet LTC6906 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Micropower, 10kHz to 1MHz Resistor Set Oscillator in SOT-23 |
| Pages / Page | 14 / 9 — APPLICATIONS INFORMATION. Guarding Against PC Board Leakage. Bypassing … |
| File Format / Size | PDF / 172 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Guarding Against PC Board Leakage. Bypassing the Power Supply
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LTC6906
APPLICATIONS INFORMATION Guarding Against PC Board Leakage Bypassing the Power Supply
The LTC6906 uses relatively large resistance values for The LTC6906 has on-chip power supply decoupling that RSET to minimize power consumption. For RSET = 1M, the eliminates the need for an external decoupling capacitor SET pin current is typically only 0.65μA. Thus, only 0.65nA in most cases. Figure 11 shows a simplified equivalent leaking into the SET pin causes a 0.1% frequency error. circuit of the output driver and on-chip decoupling network. Similarly, 1G of leakage resistance across RSET (1000 • When the output driver switches from low to high, the RSET) causes the same 0.1% error. 800pF capacitor delivers the current needed to charge the off-chip capacitive load. Within nanoseconds the system Achieving the highest accuracy requires controlling poten- power supply recharges the 800pF capacitor. tial leakage paths. PC board leakage is aggravated by both dirt and moisture. Effective cleaning is a good first step to minimizing leakage, and some PC board manufacturers LTC6906-1 V+ offer high impedance or low leakage processing options. V+ 6 fOUT Another effective method for controlling leakage is to shunt 20Ω OUT 300Ω the leakage current away from the sensitive node through 1 a low impedance path. The LTC6906 provides a signal on CLOAD 800pF the GRD pin for this purpose. Figure 10 shows a PC board GND 2 layout that uses the GRD pin and a “guard ring” to absorb ESD DIODES DRIVER DECOUPLING leakage currents. The guard ring surrounds the SET pin NETWORK 6906 F11 and the end of RSET to which it is connected. The guard ring must have no solder mask covering it to be effective.
Figure 11. Simplified Equivalent of the Output Driver
The GRD pin voltage is held within a few millivolts of the
and On-Chip Decoupling Circuit
SET pin voltage, so any leakage path between the SET pin and the guard ring generates no leakage current. Figure 12 shows a test circuit for evaluating perfor- mance of the LTC6906 with a highly inductive, 330nH power supply. Figure 13 shows the effectiveness of the LTC6906 on-chip decoupling network. For C 1 OUT V+ 6 NO SOLDER MASK LOAD = 5pF to 50pF, the OVER THE GUARD RING output waveforms remain well formed. GRD 2 GND 5 The extremely low supply current of the LTC6906 allows GUARD RING operation with substantial resistance in the power supply. 3 DIV SET 4 Figure 14 shows a test circuit for evaluating performance RSET of the LTC6906 with a highly resistive, 100Ω power sup- NO LEAKAGE CURRENT ply. Figure 15 shows the effectiveness of the on-chip decoupling network. For CLOAD = 5pF to 50pF, the output LEAKAGE waveforms remain well formed. With a 50pF load, a very CURRENT 6906 F10 small (2.5%) slow tail can be seen on the rising edge. The
Figure 10. PC Board Layout with Guard Ring
output waveform is still well formed even in this case. The ability of the LTC6906 to operate with a resistive supply permits supplying power via a CMOS logic gate or microcontroller pin. Since the LTC6906 has a turn-on time of less than 200μs, this technique can be used to enable the device only when needed and further reduce power consumption. 6906fc 9
APPLICATIONS INFORMATION Guarding Against PC Board Leakage Bypassing the Power Supply
The LTC6906 uses relatively large resistance values for The LTC6906 has on-chip power supply decoupling that RSET to minimize power consumption. For RSET = 1M, the eliminates the need for an external decoupling capacitor SET pin current is typically only 0.65μA. Thus, only 0.65nA in most cases. Figure 11 shows a simplified equivalent leaking into the SET pin causes a 0.1% frequency error. circuit of the output driver and on-chip decoupling network. Similarly, 1G of leakage resistance across RSET (1000 • When the output driver switches from low to high, the RSET) causes the same 0.1% error. 800pF capacitor delivers the current needed to charge the off-chip capacitive load. Within nanoseconds the system Achieving the highest accuracy requires controlling poten- power supply recharges the 800pF capacitor. tial leakage paths. PC board leakage is aggravated by both dirt and moisture. Effective cleaning is a good first step to minimizing leakage, and some PC board manufacturers LTC6906-1 V+ offer high impedance or low leakage processing options. V+ 6 fOUT Another effective method for controlling leakage is to shunt 20Ω OUT 300Ω the leakage current away from the sensitive node through 1 a low impedance path. The LTC6906 provides a signal on CLOAD 800pF the GRD pin for this purpose. Figure 10 shows a PC board GND 2 layout that uses the GRD pin and a “guard ring” to absorb ESD DIODES DRIVER DECOUPLING leakage currents. The guard ring surrounds the SET pin NETWORK 6906 F11 and the end of RSET to which it is connected. The guard ring must have no solder mask covering it to be effective.
Figure 11. Simplified Equivalent of the Output Driver
The GRD pin voltage is held within a few millivolts of the
and On-Chip Decoupling Circuit
SET pin voltage, so any leakage path between the SET pin and the guard ring generates no leakage current. Figure 12 shows a test circuit for evaluating perfor- mance of the LTC6906 with a highly inductive, 330nH power supply. Figure 13 shows the effectiveness of the LTC6906 on-chip decoupling network. For C 1 OUT V+ 6 NO SOLDER MASK LOAD = 5pF to 50pF, the OVER THE GUARD RING output waveforms remain well formed. GRD 2 GND 5 The extremely low supply current of the LTC6906 allows GUARD RING operation with substantial resistance in the power supply. 3 DIV SET 4 Figure 14 shows a test circuit for evaluating performance RSET of the LTC6906 with a highly resistive, 100Ω power sup- NO LEAKAGE CURRENT ply. Figure 15 shows the effectiveness of the on-chip decoupling network. For CLOAD = 5pF to 50pF, the output LEAKAGE waveforms remain well formed. With a 50pF load, a very CURRENT 6906 F10 small (2.5%) slow tail can be seen on the rising edge. The
Figure 10. PC Board Layout with Guard Ring
output waveform is still well formed even in this case. The ability of the LTC6906 to operate with a resistive supply permits supplying power via a CMOS logic gate or microcontroller pin. Since the LTC6906 has a turn-on time of less than 200μs, this technique can be used to enable the device only when needed and further reduce power consumption. 6906fc 9
