Datasheet LTC4417 (Linear Technology) - 15

LTC4417
applicaTions inForMaTion Table 1. List of Suggested P-Channel MOSFETs
V2 DISCONNECTS
MAX RATED
V2 = 18V
V1, V2, V3 MOSFET VTH(MAX) VGS(MAX) VDS(MAX) RDS(ON) AT 25°C
VOUT dVOUT I = L ≤5V Si4465ADY –1V ±8V –8V 9mΩ at –4.5V dt CL 11mΩ at –2.5V V1 VALIDATES ≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V 22mΩ at –2.5V V1 = 12V 256ms ≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V 70mΩ at –2.5V VOUT ≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V 26mΩ at –2.5V V1 = 12V ≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V VREV = ≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V 120mV V1 CONNECTS AT ≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V VOUT = 11.88V 4417 F07 ≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V
Figure 7. Reverse Current Blocking
≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V ≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V The LTC4417 validates V1 and disconnects V2, allowing ≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V VOUT to decay from 18V to 11.88V at a slew rate determined ≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V by the load current divided by the load capacitance. Once *Denotes Dual P-Channel VOUT falls to 11.88V, the LTC4417 connects V1 to VOUT.
REVERSE VOLTAGE PROTECTION SELECTING VOUT CAPACITANCE
The LTC4417 is designed to withstand reverse voltages To ensure there is minimal droop at the output, select a applied to V1, V2 and V3 with respect to V low ESR capacitor large enough to ride through the dead OUT of up to –84V. The large reverse voltage rating protects 36V input time between channel switchover. A low ESR bulk capacitor supplies and downstream devices connected to V will reduce IR drops to the output voltage while the load OUT against high reverse voltage connections of –42V (absolute current is sourced from the capacitor. Use Equation (13) maximum) with margin. to calculate the load capacitor value that will ride through the OV/UV comparator delay, tpVALID(OFF), plus the break- Select back-to-back P-channel MOSFETS with BVDSS(MAX) before-make time, tG(SWITCHOVER). ratings capable of handling any anticipated reverse voltages between V I OUT and V1, V2 or V3. Ensure transient voltage L(MAX) • t ( G(SWITCHOVER)+tpVALID(OFF)) (13) suppressors (TVS) connected to reverse connection pro- CL VOUT_DROOP(MAX) tected inputs (V1, V2 and V3) are bidirectional and input capacitors are rated for the negative voltage. where IL(MAX) is the maximum load current drawn and VOUT_DROOP(MAX) is the maximum acceptable amount of
REVERSE CURRENT BLOCKING
voltage droop at the output. When switching channels from higher voltages to lower Equation (13) assumes no inrush current limiting circuitry voltages, the REV comparator verifies the V is required. If it is required, refer to Figure 8 and use the OUT voltage is below the connecting channel’s voltage by 120mV before following Equation (14) for CL. the new channel is allowed to connect to VOUT. This ensures CL ≥ little to no reverse conduction occurs during switching. (14) I • L(MAX) (tG(SWITCHOVER) + tpVALID(OFF) + 0.79 •R •C S S ) An example is shown in Figure 7. V2 is initially connected V to V OUT _DROOP(MAX) OUT when a higher priority input supply, V1, is inserted. 4417f 15 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts