Datasheet SAM E70 (Microchip)

ManufacturerMicrochip
DescriptionSMART ARM-based Flash MCU
Pages / Page1871 / 1 — SAM E70. Atmel | SMART ARM-based Flash MCU. DATASHEET. Introduction. …
Revision12-10-2016
File Format / SizePDF / 7.8 Mb
Document Languageenglish

SAM E70. Atmel | SMART ARM-based Flash MCU. DATASHEET. Introduction. Features

Datasheet SAM E70 Microchip, Revision: 12-10-2016

Text Version of Document

link to page 3
SAM E70 Atmel | SMART ARM-based Flash MCU DATASHEET Introduction
Atmel® | SMART SAM E70 is a high-performance Flash microcontroller (MCU) based on the 32-bit ARM® Cortex®-M7 RISC (5.04 CoreMark/MHz) processor with floating point unit (FPU). The device operates at a maximum speed of 300 MHz, features up to 2048 Kbytes of Flash, dual 16 Kbytes of cache memory, up to 384 Kbytes of SRAM and is available in 64-, 100- and 144-pin packages. The Atmel | SMART SAM E70 offers an extensive peripheral set, including Ethernet 10/100, dual CAN-FD, High-speed USB Host and Device plus PHY, up to 8 UARTs, I2S, SD/MMC interface, a CMOS camera interface, system control and a 12-bit 2 Msps ADC, as well as high-performance crypto-processors AES, SHA and TRNG.
Features
Core ̶ ARM Cortex-M7 running at up to 300 MHz(1) ̶ 16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC) ̶ Simple- and double-precision HW Floating Point Unit (FPU) ̶ Memory Protection Unit (MPU) with 16 zones ̶ DSP Instructions, Thumb®-2 Instruction Set ̶ Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU) Memories ̶ Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data ̶ Up to 384 Kbytes embedded Multi-port SRAM ̶ Tightly Coupled Memory (TCM) interface with four configurations (disabled, 2 x 32 Kbytes, 2 x 64 Kbytes, 2 x 128 Kbytes) ̶ 16 Kbytes ROM with embedded Boot Loader routines (UART0, USB) and IAP routines ̶ 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling ̶ 16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling System ̶ Embedded voltage regulator for single-supply operation ̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Document Outline Introduction Features 1. Description 2. Configuration Summary 3. Block Diagram 4. Signal Description 5. Package and Pinout 5.1 144-lead Packages 5.1.1 144-pin LQFP Package Outline 5.1.2 144-ball LFBGA Package Outline 5.1.3 144-ball UFBGA Package Outline 5.2 144-lead Package Pinout 5.3 100-lead Packages 5.3.1 100-pin LQFP Package Outline 5.3.2 100-ball TFBGA Package Outline 5.4 100-lead Package Pinout 5.5 64-lead Package 5.5.1 64-pin LQFP Package Outline 5.6 64-lead Package Pinout 6. Power Considerations 6.1 Power Supplies 6.2 Power Constraints 6.2.1 Power-up 6.2.2 Power-down 6.3 Voltage Regulator 6.4 Backup SRAM Power Switch 6.5 Active Mode 6.6 Low-power Modes 6.6.1 Backup Mode 6.6.2 Wait Mode 6.6.3 Sleep Mode 6.6.4 Low-Power Mode Summary Table 6.7 Wake-up Sources 6.8 Fast Startup 7. Input/Output Lines 7.1 General-Purpose I/O Lines 7.2 System I/O Lines 7.2.1 Serial Wire Debug Port (SW-DP) Pins 7.2.2 Embedded Trace Module (ETM) Pins 7.3 NRST Pin 7.4 ERASE Pin 8. Interconnect 9. Product Mapping 10. Memories 10.1 Embedded Memories 10.1.1 Internal SRAM 10.1.2 Tightly Coupled Memory (TCM) Interface 10.1.3 Internal ROM 10.1.4 Backup SRAM 10.1.5 Flash Memories 10.1.5.1 Embedded Flash Overview 10.1.5.2 Enhanced Embedded Flash Controller 10.1.5.3 Flash Speed 10.1.5.4 Lock Regions 10.1.5.5 Security Bit Feature 10.1.5.6 Unique Identifier 10.1.5.7 User Signature 10.1.5.8 Fast Flash Programming Interface 10.1.5.9 SAM-BA Boot 10.1.5.10 General-purpose NVM (GPNVM) Bits 10.1.6 Boot Strategies 10.2 External Memories 11. Event System 11.1 Embedded Characteristics 11.2 Real-time Event Mapping 12. System Controller 12.1 System Controller and Peripherals Mapping 12.2 Power-on-Reset, Brownout and Supply Monitor 12.2.1 Power-on-Reset 12.2.2 Brownout Detector on VDDCORE 12.2.3 Supply Monitor on VDDIO 12.3 Reset Controller 13. Peripherals 13.1 Peripheral Identifiers 13.2 Peripheral Signal Multiplexing on I/O Lines 14. ARM Cortex-M7 Processor 14.1 Description 14.1.1 System-Level Interface 14.1.2 Integrated Configurable Debug 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Programmer’s Model 14.4.1 Processor Modes and Privilege Levels for Software Execution 14.4.2 Stacks 14.4.2.1 Processor Core Registers 14.4.3 General-purpose Registers 14.4.4 Stack Pointer 14.4.5 Link Register 14.4.6 Program Counter 14.4.6.1 Program Status Register 14.4.6.2 Application Program Status Register 14.4.6.3 Interrupt Program Status Register 14.4.6.4 Execution Program Status Register 14.4.6.5 Exception Mask Registers 14.4.6.6 Priority Mask Register 14.4.6.7 Fault Mask Register 14.4.6.8 Base Priority Mask Register 14.4.6.9 Control Register 14.4.6.10 Exceptions and Interrupts 14.4.6.11 Data Types 14.4.6.12 Cortex Microcontroller Software Interface Standard (CMSIS) 14.5 ARM Cortex-M7 Configuration 15. Debug and Test Features 15.1 Description 15.2 Embedded Characteristics 15.3 Associated Documents 15.4 Debug and Test Block Diagram 15.5 Debug and Test Pin Description 15.6 Application Examples 15.6.1 Debug Environment 15.6.2 Test Environment 15.7 Functional Description 15.7.1 Test Pin 15.7.2 Debug Architecture 15.7.3 Serial Wire Debug Port (SW-DP) Pins 15.7.4 Embedded Trace Module (ETM) Pins 15.7.5 Flash Patch Breakpoint (FPB) 15.7.6 Data Watchpoint and Trace (DWT) 15.7.7 Instrumentation Trace Macrocell (ITM) 15.7.7.1 How to Configure the ITM 15.7.7.2 Asynchronous Mode 15.7.7.3 How to Configure the TPIU 15.7.8 IEEE1149.1 JTAG Boundary Scan 15.7.8.1 JTAG Boundary Scan Register 15.7.9 ID Code Register 16. SAM-BA Boot Program 16.1 Description 16.2 Embedded Characteristics 16.3 Hardware and Software Constraints 16.4 Flow Diagram 16.5 Device Initialization 16.6 SAM-BA Monitor 16.6.1 UART0 Serial Port 16.6.2 Xmodem Protocol 16.6.3 USB Device Port 16.6.3.1 Enumeration Process 16.6.3.2 Communication Endpoints 16.6.4 In Application Programming (IAP) Feature 17. Fast Flash Programming Interface (FFPI) 17.1 Description 17.2 Embedded Characteristics 17.3 Parallel Fast Flash Programming 17.3.1 Device Configuration 17.3.2 Signal Names 17.3.3 Entering Parallel Programming Mode 17.3.4 Programmer Handshaking 17.3.4.1 Write Handshaking 17.3.4.2 Read Handshaking 17.3.5 Device Operations 17.3.5.1 Flash Read Command 17.3.5.2 Flash Write Command 17.3.5.3 Flash Full Erase Command 17.3.5.4 Flash Lock Commands 17.3.5.5 Flash General-purpose NVM Commands 17.3.5.6 Flash Security Bit Command 17.3.5.7 Memory Write Command 17.3.5.8 Get Version Command 18. Bus Matrix (MATRIX) 18.1 Description 18.2 Embedded Characteristics 18.2.1 Matrix Masters 18.2.2 Matrix Slaves 18.2.3 Master to Slave Access 18.3 Functional Description 18.3.1 Memory Mapping 18.3.2 Special Bus Granting Mechanism 18.3.2.1 No Default Master 18.3.2.2 Last Access Master 18.3.2.3 Fixed Default Master 18.3.3 Arbitration 18.3.3.1 Arbitration Rules Undefined Length Burst Arbitration Slot Cycle Limit Arbitration 18.3.3.2 Arbitration Priority Scheme Fixed Priority Arbitration Round-Robin Arbitration 18.3.4 System I/O Configuration 18.3.5 SMC NAND Flash Chip Select Configuration 18.3.6 Register Write Protection 18.4 Bus Matrix (MATRIX) User Interface 18.4.1 Bus Matrix Master Configuration Registers 18.4.2 Bus Matrix Slave Configuration Registers 18.4.3 Bus Matrix Priority Registers A For Slaves 18.4.4 Bus Matrix Priority Registers B For Slaves 18.4.5 Bus Matrix Master Remap Control Register 18.4.6 CAN0 Configuration Register 18.4.7 System I/O and CAN1 Configuration Register 18.4.8 SMC NAND Flash Chip Select Configuration Register 18.4.9 Write Protection Mode Register 18.4.10 Write Protection Status Register 19. USB Transmitter Macrocell Interface (UTMI) 19.1 Description 19.2 Embedded Characteristics 19.3 USB Transmitter Macrocell Interface (UTMI) User Interface 19.3.1 OHCI Interrupt Configuration Register 19.3.2 UTMI Clock Trimming Register 20. Chip Identifier (CHIPID) 20.1 Description 20.2 Embedded Characteristics 20.3 Chip Identifier (CHIPID) User Interface 20.3.1 Chip ID Register 20.3.2 Chip ID Extension Register 21. Enhanced Embedded Flash Controller (EEFC) 21.1 Description 21.2 Embedded Characteristics 21.3 Product Dependencies 21.3.1 Power Management 21.3.2 Interrupt Sources 21.4 Functional Description 21.4.1 Embedded Flash Organization 21.4.2 Read Operations 21.4.2.1 Code Read Optimization 21.4.2.2 Code Loop Optimization 21.4.2.3 Data Read Optimization 21.4.3 Flash Commands 21.4.3.1 Get Flash Descriptor Command 21.4.3.2 Write Commands Full Page Programming Partial Page Programming Optimized Partial Page Programming Programming Bytes 21.4.3.3 Erase Commands 21.4.3.4 Lock Bit Protection 21.4.3.5 GPNVM Bit 21.4.3.6 Calibration Bit 21.4.3.7 Security Bit Protection 21.4.3.8 Unique Identifier Area 21.4.3.9 User Signature Area 21.4.3.10 ECC Errors and Corrections 21.4.4 Register Write Protection 21.5 Enhanced Embedded Flash Controller (EEFC) User Interface 21.5.1 EEFC Flash Mode Register 21.5.2 EEFC Flash Command Register 21.5.3 EEFC Flash Status Register 21.5.4 EEFC Flash Result Register 21.5.5 EEFC Write Protection Mode Register 22. Supply Controller (SUPC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Functional Description 22.4.1 Overview 22.4.2 Slow Clock Generator 22.4.3 Core Voltage Regulator Control/Backup Low-power Mode 22.4.4 Using Backup Batteries/Backup Supply 22.4.5 Supply Monitor 22.4.6 Backup Power Supply Reset 22.4.6.1 Raising the Backup Power Supply 22.4.7 Core Reset 22.4.7.1 Supply Monitor Reset 22.4.7.2 Brownout Detector Reset 22.4.8 Controlling the SRAM Power Supply 22.4.9 Wake-up Sources 22.4.9.1 Wake-up Inputs 22.4.9.2 Low-power Tamper Detection and Anti-Tampering 22.4.9.3 Clock Alarms 22.4.9.4 Supply Monitor Detection 22.4.10 Register Write Protection 22.4.11 Register Bits in Backup Domain (VDDIO) 22.5 Supply Controller (SUPC) User Interface 22.5.1 System Controller (SYSC) User Interface 22.5.2 Supply Controller (SUPC) User Interface 22.5.3 Supply Controller Control Register 22.5.4 Supply Controller Supply Monitor Mode Register 22.5.5 Supply Controller Mode Register 22.5.6 Supply Controller Wake-up Mode Register 22.5.7 Supply Controller Wake-up Inputs Register 22.5.8 Supply Controller Status Register 22.5.9 System Controller Write Protection Mode Register 23. Watchdog Timer (WDT) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Functional Description 23.5 Watchdog Timer (WDT) User Interface 23.5.1 Watchdog Timer Control Register 23.5.2 Watchdog Timer Mode Register 23.5.3 Watchdog Timer Status Register 24. Reinforced Safety Watchdog Timer (RSWDT) 24.1 Description 24.2 Embedded Characteristics 24.3 Block Diagram 24.4 Functional Description 24.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface 24.5.1 Reinforced Safety Watchdog Timer Control Register 24.5.2 Reinforced Safety Watchdog Timer Mode Register 24.5.3 Reinforced Safety Watchdog Timer Status Register 25. Reset Controller (RSTC) 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 Functional Description 25.4.1 Reset Controller Overview 25.4.2 NRST Manager 25.4.2.1 NRST Signal or Interrupt 25.4.2.2 NRST External Reset Control 25.4.3 Reset States 25.4.3.1 General Reset 25.4.3.2 Backup Reset 25.4.3.3 Watchdog Reset 25.4.3.4 Software Reset 25.4.3.5 User Reset 25.4.4 Reset State Priorities 25.5 Reset Controller (RSTC) User Interface 25.5.1 Reset Controller Control Register 25.5.2 Reset Controller Status Register 25.5.3 Reset Controller Mode Register 26. Real-time Clock (RTC) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Product Dependencies 26.4.1 Power Management 26.4.2 Interrupt 26.5 Functional Description 26.5.1 Reference Clock 26.5.2 Timing 26.5.3 Alarm 26.5.4 Error Checking when Programming 26.5.5 RTC Internal Free Running Counter Error Checking 26.5.6 Updating Time/Calendar 26.5.7 RTC Accurate Clock Calibration 26.5.8 Waveform Generation 26.6 Real-time Clock (RTC) User Interface 26.6.1 RTC Control Register 26.6.2 RTC Mode Register 26.6.3 RTC Time Register 26.6.4 RTC Calendar Register 26.6.5 RTC Time Alarm Register 26.6.6 RTC Calendar Alarm Register 26.6.7 RTC Status Register 26.6.8 RTC Status Clear Command Register 26.6.9 RTC Interrupt Enable Register 26.6.10 RTC Interrupt Disable Register 26.6.11 RTC Interrupt Mask Register 26.6.12 RTC Valid Entry Register 26.6.13 RTC Write Protection Mode Register 27. Real-time Timer (RTT) 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Functional Description 27.5 Real-time Timer (RTT) User Interface 27.5.1 Real-timeTimer Mode Register 27.5.2 Real-time Timer Alarm Register 27.5.3 Real-time Timer Value Register 27.5.4 Real-time Timer Status Register 28. SDRAM Controller (SDRAMC) 28.1 Description 28.2 Embedded Characteristics 28.3 Signal Description 28.4 Software Interface/SDRAM Organization, Address Mapping 28.4.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width 28.5 Product Dependencies 28.5.1 SDRAM Device Initialization 28.5.2 I/O Lines 28.5.3 Power Management 28.5.4 Interrupt Sources 28.6 Functional Description 28.6.1 SDRAM Controller Write Cycle 28.6.2 SDRAM Controller Read Cycle 28.6.3 Border Management 28.6.4 SDRAM Controller Refresh Cycles 28.6.5 Power Management 28.6.5.1 Self-refresh Mode 28.6.5.2 Low-power Mode 28.6.5.3 Deep Power-down Mode 28.6.6 Scrambling/Unscrambling Function 28.7 SDRAM Controller (SDRAMC) User Interface 28.7.1 SDRAMC Mode Register 28.7.2 SDRAMC Refresh Timer Register 28.7.3 SDRAMC Configuration Register 28.7.4 SDRAMC Low Power Register 28.7.5 SDRAMC Interrupt Enable Register 28.7.6 SDRAMC Interrupt Disable Register 28.7.7 SDRAMC Interrupt Mask Register 28.7.8 SDRAMC Interrupt Status Register 28.7.9 SDRAMC Memory Device Register 28.7.10 SDRAMC Configuration Register 1 28.7.11 SDRAMC OCMS Register 28.7.12 SDRAMC OCMS KEY1 Register 28.7.13 SDRAMC OCMS KEY2 Register 29. General Purpose Backup Registers (GPBR) 29.1 Description 29.2 Embedded Characteristics 29.3 General Purpose Backup Registers (GPBR) User Interface 29.3.1 General Purpose Backup Register x 30. Clock Generator 30.1 Description 30.2 Embedded Characteristics 30.3 Block Diagram 30.4 Slow Clock 30.4.1 Embedded 32 kHz (typical) RC Oscillator 30.4.2 32.768 kHz Crystal Oscillator 30.5 Main Clock 30.5.1 Embedded 4/8/12 MHz RC Oscillator 30.5.2 4/8/12 MHz RC Oscillator Clock Frequency Adjustment 30.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator 30.5.4 Main Clock Source Selection 30.5.5 Bypassing the Main Crystal Oscillator 30.5.6 Main Clock Frequency Counter 30.5.7 Switching Main Clock between the RC Oscillator and Crystal Oscillator 30.6 Divider and PLL Block 30.6.1 Divider and Phase Lock Loop Programming 30.7 UTMI Phase Lock Loop Programming 31. Power Management Controller (PMC) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Master Clock Controller 31.5 Processor Clock Controller 31.6 SysTick External Clock 31.7 USB Clock Controller 31.8 Peripheral Clock Controller 31.9 Asynchronous Partial Wake-up 31.9.1 Description 31.9.2 Asynchronous Partial Wake-up in Wait Mode (SleepWalking) 31.9.2.1 Configuration Procedure 31.9.3 Asynchronous Partial Wake-Up in Active Mode 31.9.3.1 Configuration Procedure 31.10 Free-Running Processor Clock 31.11 Programmable Clock Output Controller 31.12 Core and Bus Independent Clocks for Peripherals 31.13 Fast Startup 31.14 Startup from Embedded Flash 31.15 Main Clock Failure Detection 31.16 32.768 kHz Crystal Oscillator Frequency Monitor 31.17 Programming Sequence 31.18 Clock Switching Details 31.18.1 Master Clock Switching Timings 31.18.2 Clock Switching Waveforms 31.19 Register Write Protection 31.20 Power Management Controller (PMC) User Interface 31.20.1 PMC System Clock Enable Register 31.20.2 PMC System Clock Disable Register 31.20.3 PMC System Clock Status Register 31.20.4 PMC Peripheral Clock Enable Register 0 31.20.5 PMC Peripheral Clock Disable Register 0 31.20.6 PMC Peripheral Clock Status Register 0 31.20.7 PMC UTMI Clock Configuration Register 31.20.8 PMC Clock Generator Main Oscillator Register 31.20.9 PMC Clock Generator Main Clock Frequency Register 31.20.10 PMC Clock Generator PLLA Register 31.20.11 PMC Master Clock Register 31.20.12 PMC USB Clock Register 31.20.13 PMC Programmable Clock Register 31.20.14 PMC Interrupt Enable Register 31.20.15 PMC Interrupt Disable Register 31.20.16 PMC Status Register 31.20.17 PMC Interrupt Mask Register 31.20.18 PMC Fast Startup Mode Register 31.20.19 PMC Fast Startup Polarity Register 31.20.20 PMC Fault Output Clear Register 31.20.21 PMC Write Protection Mode Register 31.20.22 PMC Write Protection Status Register 31.20.23 PMC Peripheral Clock Enable Register 1 31.20.24 PMC Peripheral Clock Disable Register 1 31.20.25 PMC Peripheral Clock Status Register 1 31.20.26 PMC Peripheral Control Register 31.20.27 PMC Oscillator Calibration Register 31.20.28 PMC SleepWalking Enable Register 0 31.20.29 PMC SleepWalking Enable Register 1 31.20.30 PMC SleepWalking Disable Register 0 31.20.31 PMC SleepWalking Disable Register 1 31.20.32 PMC SleepWalking Status Register 0 31.20.33 PMC SleepWalking Status Register 1 31.20.34 PMC SleepWalking Activity Status Register 0 31.20.35 PLL Maximum Multiplier Value Register 31.20.36 PMC SleepWalking Activity Status Register 1 31.20.37 PMC SleepWalking Activity In Progress Register 32. Parallel Input/Output Controller (PIO) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 Product Dependencies 32.4.1 Pin Multiplexing 32.4.2 External Interrupt Lines 32.4.3 Power Management 32.4.4 Interrupt Sources 32.5 Functional Description 32.5.1 Pull-up and Pull-down Resistor Control 32.5.2 I/O Line or Peripheral Function Selection 32.5.3 Peripheral A or B or C or D Selection 32.5.4 Output Control 32.5.5 Synchronous Data Output 32.5.6 Multi-Drive Control (Open Drain) 32.5.7 Output Line Timings 32.5.8 Inputs 32.5.9 Input Glitch and Debouncing Filters 32.5.10 Input Edge/Level Interrupt 32.5.11 I/O Lines Lock 32.5.12 Programmable I/O Drive 32.5.13 Programmable Schmitt Trigger 32.5.14 Parallel Capture Mode 32.5.14.1 Overview 32.5.14.2 Functional Description 32.5.14.3 Restrictions 32.5.14.4 Programming Sequence 32.5.15 I/O Lines Programming Example 32.5.16 Register Write Protection 32.6 Parallel Input/Output Controller (PIO) User Interface 32.6.1 PIO Enable Register 32.6.2 PIO Disable Register 32.6.3 PIO Status Register 32.6.4 PIO Output Enable Register 32.6.5 PIO Output Disable Register 32.6.6 PIO Output Status Register 32.6.7 PIO Input Filter Enable Register 32.6.8 PIO Input Filter Disable Register 32.6.9 PIO Input Filter Status Register 32.6.10 PIO Set Output Data Register 32.6.11 PIO Clear Output Data Register 32.6.12 PIO Output Data Status Register 32.6.13 PIO Pin Data Status Register 32.6.14 PIO Interrupt Enable Register 32.6.15 PIO Interrupt Disable Register 32.6.16 PIO Interrupt Mask Register 32.6.17 PIO Interrupt Status Register 32.6.18 PIO Multi-driver Enable Register 32.6.19 PIO Multi-driver Disable Register 32.6.20 PIO Multi-driver Status Register 32.6.21 PIO Pull-Up Disable Register 32.6.22 PIO Pull-Up Enable Register 32.6.23 PIO Pull-Up Status Register 32.6.24 PIO Peripheral ABCD Select Register 1 32.6.25 PIO Peripheral ABCD Select Register 2 32.6.26 PIO Input Filter Slow Clock Disable Register 32.6.27 PIO Input Filter Slow Clock Enable Register 32.6.28 PIO Input Filter Slow Clock Status Register 32.6.29 PIO Slow Clock Divider Debouncing Register 32.6.30 PIO Pad Pull-Down Disable Register 32.6.31 PIO Pad Pull-Down Enable Register 32.6.32 PIO Pad Pull-Down Status Register 32.6.33 PIO Output Write Enable Register 32.6.34 PIO Output Write Disable Register 32.6.35 PIO Output Write Status Register 32.6.36 PIO Additional Interrupt Modes Enable Register 32.6.37 PIO Additional Interrupt Modes Disable Register 32.6.38 PIO Additional Interrupt Modes Mask Register 32.6.39 PIO Edge Select Register 32.6.40 PIO Level Select Register 32.6.41 PIO Edge/Level Status Register 32.6.42 PIO Falling Edge/Low-Level Select Register 32.6.43 PIO Rising Edge/High-Level Select Register 32.6.44 PIO Fall/Rise - Low/High Status Register 32.6.45 PIO Lock Status Register 32.6.46 PIO Write Protection Mode Register 32.6.47 PIO Write Protection Status Register 32.6.48 PIO Schmitt Trigger Register 32.6.49 PIO I/O Drive Register 32.6.50 PIO Parallel Capture Mode Register 32.6.51 PIO Parallel Capture Interrupt Enable Register 32.6.52 PIO Parallel Capture Interrupt Disable Register 32.6.53 PIO Parallel Capture Interrupt Mask Register 32.6.54 PIO Parallel Capture Interrupt Status Register 32.6.55 PIO Parallel Capture Reception Holding Register 33. External Bus Interface (EBI) 33.1 Description 33.2 Embedded Characteristics 33.3 EBI Block Diagram 33.4 I/O Lines Description 33.5 Application Example 33.5.1 Hardware Interface 33.5.2 Product Dependencies 33.5.2.1 I/O Lines 33.5.3 Functional Description 33.5.3.1 Bus Multiplexing 33.5.3.2 Static Memory Controller 33.5.3.3 SDRAM Controller 33.5.3.4 NAND Flash Support 33.5.4 Implementation Examples 33.5.4.1 16-bit SDRAM on NCS1 34. Static Memory Controller (SMC) 34.1 Description 34.2 Embedded Characteristics 34.3 I/O Lines Description 34.4 Multiplexed Signals 34.5 Product Dependencies 34.5.1 I/O Lines 34.5.2 Power Management 34.6 External Memory Mapping 34.7 Connection to External Devices 34.7.1 Data Bus Width 34.7.2 Byte Write or Byte Select Access 34.7.2.1 Byte Write Access 34.7.2.2 Byte Select Access 34.7.2.3 Signal Multiplexing 34.7.3 NAND Flash Support 34.8 Application Example 34.8.1 Implementation Examples 34.8.1.1 8-bit NAND Flash Hardware Configuration Software Configuration 34.8.1.2 NOR Flash Hardware Configuration Software Configuration 34.9 Standard Read and Write Protocols 34.9.1 Read Waveforms 34.9.1.1 NRD Waveform 34.9.1.2 NCS Waveform 34.9.1.3 Read Cycle 34.9.1.4 Null Delay Setup and Hold 34.9.1.5 Null Pulse 34.9.2 Read Mode 34.9.2.1 Read is Controlled by NRD (SMC_MODE.READ_MODE = 1): 34.9.2.2 Read is Controlled by NCS (SMC_MODE.READ_MODE = 0) 34.9.3 Write Waveforms 34.9.3.1 NWE Waveforms 34.9.3.2 NCS Waveforms 34.9.3.3 Write Cycle 34.9.3.4 Null Delay Setup and Hold 34.9.3.5 Null Pulse 34.9.4 Write Mode 34.9.4.1 Write is Controlled by NWE (SMC.MODE.WRITE_MODE = 1): 34.9.4.2 Write is Controlled by NCS (SMC.MODE.WRITE_MODE = 0) 34.9.5 Register Write Protection 34.9.6 Coding Timing Parameters 34.9.7 Reset Values of Timing Parameters 34.9.8 Usage Restriction 34.10 Scrambling/Unscrambling Function 34.11 Automatic Wait States 34.11.1 Chip Select Wait States 34.11.2 Early Read Wait State 34.11.3 Reload User Configuration Wait State 34.11.3.1 User Procedure 34.11.3.2 Slow Clock Mode Transition 34.11.4 Read to Write Wait State 34.12 Data Float Wait States 34.12.1 SMC_MODE.READ_MODE 34.12.2 TDF Optimization Enabled (SMC_MODE.TDF_MODE = 1) 34.12.3 TDF Optimization Disabled (SMC_MODE.TDF_MODE = 0) 34.13 External Wait 34.13.1 Restriction 34.13.2 Frozen Mode 34.13.3 Ready Mode 34.13.4 NWAIT Latency and Read/Write Timings 34.14 Slow Clock Mode 34.14.1 Slow Clock Mode Waveforms 34.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 34.15 Asynchronous Page Mode 34.15.1 Protocol and Timings in Page Mode 34.15.2 Page Mode Restriction 34.15.3 Sequential and Non-sequential Accesses 34.16 Static Memory Controller (SMC) User Interface 34.16.1 SMC Setup Register 34.16.2 SMC Pulse Register 34.16.3 SMC Cycle Register 34.16.4 SMC Mode Register 34.16.5 SMC Off-Chip Memory Scrambling Register 34.16.6 SMC Off-Chip Memory Scrambling Key1 Register 34.16.7 SMC Off-Chip Memory Scrambling Key2 Register 34.16.8 SMC Write Protection Mode Register 34.16.9 SMC Write Protection Status Register 35. DMA Controller (XDMAC) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 DMA Controller Peripheral Connections 35.5 Functional Description 35.5.1 Basic Definitions 35.5.2 Transfer Hierarchy Diagram 35.5.3 Peripheral Synchronized Transfer 35.5.3.1 Software Triggered Synchronized Transfer 35.5.4 XDMAC Transfer Software Operation 35.5.4.1 Single Block With Single Microblock Transfer 35.5.4.2 Single Block Transfer With Multiple Microblock 35.5.4.3 Master Transfer 35.5.4.4 Disabling A Channel Before Transfer Completion 35.6 Linked List Descriptor Operation 35.6.1 Linked List Descriptor View 35.6.1.1 Channel Next Descriptor View 0–3 Structures 35.6.2 Descriptor Structure Members Description 35.6.2.1 Descriptor Structure Microblock Control Member 35.7 XDMAC Maintenance Software Operations 35.7.1 Disabling a Channel 35.7.2 Suspending a Channel 35.7.3 Flushing a Channel 35.7.4 Maintenance Operation Priority 35.7.4.1 Disable Operation Priority 35.7.4.2 Flush Operation Priority 35.7.4.3 Suspend Operation Priority 35.8 XDMAC Software Requirements 35.9 Extensible DMA Controller (XDMAC) User Interface 35.9.1 XDMAC Global Type Register 35.9.2 XDMAC Global Configuration Register 35.9.3 XDMAC Global Weighted Arbiter Configuration Register 35.9.4 XDMAC Global Interrupt Enable Register 35.9.5 XDMAC Global Interrupt Disable Register 35.9.6 XDMAC Global Interrupt Mask Register 35.9.7 XDMAC Global Interrupt Status Register 35.9.8 XDMAC Global Channel Enable Register 35.9.9 XDMAC Global Channel Disable Register 35.9.10 XDMAC Global Channel Status Register 35.9.11 XDMAC Global Channel Read Suspend Register 35.9.12 XDMAC Global Channel Write Suspend Register 35.9.13 XDMAC Global Channel Read Write Suspend Register 35.9.14 XDMAC Global Channel Read Write Resume Register 35.9.15 XDMAC Global Channel Software Request Register 35.9.16 XDMAC Global Channel Software Request Status Register 35.9.17 XDMAC Global Channel Software Flush Request Register 35.9.18 XDMAC Channel x [x = 0..23] Interrupt Enable Register 35.9.19 XDMAC Channel x [x = 0..23] Interrupt Disable Register 35.9.20 XDMAC Channel x [x = 0..23] Interrupt Mask Register 35.9.21 XDMAC Channel x [x = 0..23] Interrupt Status Register 35.9.22 XDMAC Channel x [x = 0..23] Source Address Register 35.9.23 XDMAC Channel x [x = 0..23] Destination Address Register 35.9.24 XDMAC Channel x [x = 0..23] Next Descriptor Address Register 35.9.25 XDMAC Channel x [x = 0..23] Next Descriptor Control Register 35.9.26 XDMAC Channel x [x = 0..23] Microblock Control Register 35.9.27 XDMAC Channel x [x = 0..23] Block Control Register 35.9.28 XDMAC Channel x [x = 0..23] Configuration Register 35.9.29 XDMAC Channel x [x = 0..23] Data Stride Memory Set Pattern Register 35.9.30 XDMAC Channel x [x = 0..23] Source Microblock Stride Register 35.9.31 XDMAC Channel x [x = 0..23] Destination Microblock Stride Register 36. Image Sensor Interface (ISI) 36.1 Description 36.2 Embedded Characteristics 36.3 Block Diagram 36.4 Product Dependencies 36.4.1 I/O Lines 36.4.2 Power Management 36.4.3 Interrupt Sources 36.5 Functional Description 36.5.1 Data Timing 36.5.1.1 VSYNC/HSYNC Data Timing 36.5.1.2 SAV/EAV Data Timing 36.5.2 Data Ordering 36.5.3 Clocks 36.5.4 Preview Path 36.5.4.1 Scaling, Decimation (Subsampling) 36.5.4.2 Color Space Conversion 36.5.4.3 Memory Interface RGB Mode 12-bit Grayscale Mode 8-bit Grayscale Mode 36.5.4.4 FIFO and DMA Features 36.5.5 Codec Path 36.5.5.1 Color Space Conversion 36.5.5.2 Memory Interface 36.5.5.3 DMA Features 36.6 Image Sensor Interface (ISI) User Interface 36.6.1 ISI Configuration 1 Register 36.6.2 ISI Configuration 2 Register 36.6.3 ISI Preview Size Register 36.6.4 ISI Preview Decimation Factor Register 36.6.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register 36.6.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register 36.6.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register 36.6.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register 36.6.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register 36.6.10 ISI Control Register 36.6.11 ISI Status Register 36.6.12 ISI Interrupt Enable Register 36.6.13 ISI Interrupt Disable Register 36.6.14 ISI Interrupt Mask Register 36.6.15 DMA Channel Enable Register 36.6.16 DMA Channel Disable Register 36.6.17 DMA Channel Status Register 36.6.18 DMA Preview Base Address Register 36.6.19 DMA Preview Control Register 36.6.20 DMA Preview Descriptor Address Register 36.6.21 DMA Codec Base Address Register 36.6.22 DMA Codec Control Register 36.6.23 DMA Codec Descriptor Address Register 36.6.24 ISI Write Protection Mode Register 36.6.25 ISI Write Protection Status Register 37. USB High-Speed Interface (USBHS) 37.1 Description 37.2 Embedded Characteristics 37.3 Block Diagram 37.3.1 Signal Description 37.4 Product Dependencies 37.4.1 I/O Lines 37.4.2 Clocks 37.4.3 Interrupt Sources 37.4.4 USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA) 37.5 Functional Description 37.5.1 USB General Operation 37.5.1.1 Power-On and Reset 37.5.1.2 Interrupts 37.5.1.3 MCU Power Modes USB Suspend Mode Clock Frozen 37.5.1.4 Speed Control Device Mode Host Mode 37.5.1.5 DPRAM Management 37.5.1.6 Pad Suspend 37.5.2 USB Device Operation 37.5.2.1 Introduction 37.5.2.2 Power-On and Reset 37.5.2.3 USB Reset 37.5.2.4 Endpoint Reset 37.5.2.5 Endpoint Activation 37.5.2.6 Address Setup 37.5.2.7 Suspend and Wake-up 37.5.2.8 Detach 37.5.2.9 Remote Wake-up 37.5.2.10 STALL Request Special Considerations for Control Endpoints STALL Handshake and Retry Mechanism 37.5.2.11 Management of Control Endpoints Overview Control Write Control Read 37.5.2.12 Management of IN Endpoints Overview Detailed Description 37.5.2.13 Management of OUT Endpoints Overview Detailed Description 37.5.2.14 Underflow 37.5.2.15 Overflow 37.5.2.16 HB IsoIn Error 37.5.2.17 HB IsoFlush 37.5.2.18 CRC Error 37.5.2.19 Interrupts Global Interrupts Endpoint Interrupts DMA Interrupts 37.5.2.20 Test Modes 37.5.3 USB Host Operation 37.5.3.1 Description of Pipes 37.5.3.2 Power-On and Reset 37.5.3.3 Device Detection 37.5.3.4 USB Reset 37.5.3.5 Pipe Reset 37.5.3.6 Pipe Activation 37.5.3.7 Address Setup 37.5.3.8 Remote Wake-up 37.5.3.9 Management of Control Pipes 37.5.3.10 Management of IN Pipes 37.5.3.11 Management of OUT Pipes 37.5.3.12 CRC Error 37.5.3.13 Interrupts Global Interrupts Pipe Interrupts DMA Interrupts 37.5.4 USB DMA Operation 37.5.5 USB DMA Channel Transfer Descriptor 37.6 USB High-Speed (USBHS) User Interface 37.6.1 General Control Register 37.6.2 General Status Register 37.6.3 General Status Clear Register 37.6.4 General Status Set Register 37.6.5 Device General Control Register 37.6.6 Device Global Interrupt Status Register 37.6.7 Device Global Interrupt Clear Register 37.6.8 Device Global Interrupt Set Register 37.6.9 Device Global Interrupt Mask Register 37.6.10 Device Global Interrupt Disable Register 37.6.11 Device Global Interrupt Enable Register 37.6.12 Device Endpoint Register 37.6.13 Device Frame Number Register 37.6.14 Device Endpoint x Configuration Register 37.6.15 Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints) 37.6.16 Device Endpoint x Status Register (Isochronous Endpoints) 37.6.17 Device Endpoint x Clear Register (Control, Bulk, Interrupt Endpoints) 37.6.18 Device Endpoint x Clear Register (Isochronous Endpoints) 37.6.19 Device Endpoint x Set Register (Control, Bulk, Interrupt Endpoints) 37.6.20 Device Endpoint x Set Register (Isochronous Endpoints) 37.6.21 Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints) 37.6.22 Device Endpoint x Mask Register (Isochronous Endpoints) 37.6.23 Device Endpoint x Disable Register (Control, Bulk, Interrupt Endpoints) 37.6.24 Device Endpoint x Disable Register (Isochronous Endpoints) 37.6.25 Device Endpoint x Enable Register (Control, Bulk, Interrupt Endpoints) 37.6.26 Device Endpoint x Enable Register (Isochronous Endpoints) 37.6.27 Device DMA Channel x Next Descriptor Address Register 37.6.28 Device DMA Channel x Address Register 37.6.29 Device DMA Channel x Control Register 37.6.30 Device DMA Channel x Status Register 37.6.31 Host General Control Register 37.6.32 Host Global Interrupt Status Register 37.6.33 Host Global Interrupt Clear Register 37.6.34 Host Global Interrupt Set Register 37.6.35 Host Global Interrupt Mask Register 37.6.36 Host Global Interrupt Disable Register 37.6.37 Host Global Interrupt Enable Register 37.6.38 Host Frame Number Register 37.6.39 Host Address 1 Register 37.6.40 Host Address 2 Register 37.6.41 Host Address 3 Register 37.6.42 Host Pipe Register 37.6.43 Host Pipe x Configuration Register 37.6.44 Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe) 37.6.45 Host Pipe x Status Register (Control, Bulk Pipes) 37.6.46 Host Pipe x Status Register (Interrupt Pipes) 37.6.47 Host Pipe x Status Register (Isochronous Pipes) 37.6.48 Host Pipe x Clear Register (Control, Bulk Pipes) 37.6.49 Host Pipe x Clear Register (Interrupt Pipes) 37.6.50 Host Pipe x Clear Register (Isochronous Pipes) 37.6.51 Host Pipe x Set Register (Control, Bulk Pipes) 37.6.52 Host Pipe x Set Register (Interrupt Pipes) 37.6.53 Host Pipe x Set Register (Isochronous Pipes) 37.6.54 Host Pipe x Mask Register (Control, Bulk Pipes) 37.6.55 Host Pipe x Mask Register (Interrupt Pipes) 37.6.56 Host Pipe x Mask Register (Isochronous Pipes) 37.6.57 Host Pipe x Disable Register (Control, Bulk Pipes) 37.6.58 Host Pipe x Disable Register (Interrupt Pipes) 37.6.59 Host Pipe x Disable Register (Isochronous Pipes) 37.6.60 Host Pipe x Enable Register (Control, Bulk Pipes) 37.6.61 Host Pipe x Enable Register (Interrupt Pipes) 37.6.62 Host Pipe x Enable Register (Isochronous Pipes) 37.6.63 Host Pipe x IN Request Register 37.6.64 Host Pipe x Error Register 37.6.65 Host DMA Channel x Next Descriptor Address Register 37.6.66 Host DMA Channel x Address Register 37.6.67 Host DMA Channel x Control Register 37.6.68 Host DMA Channel x Status Register 38. Ethernet MAC (GMAC) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 Signal Interface 38.5 Product Dependencies 38.5.1 I/O Lines 38.5.2 Power Management 38.5.3 Interrupt Sources 38.6 Functional Description 38.6.1 Media Access Controller 38.6.2 1588 Time Stamp Unit 38.6.3 AHB Direct Memory Access Interface 38.6.3.1 Packet Buffer DMA 38.6.3.2 Partial Store and Forward Using Packet Buffer DMA 38.6.3.3 Receive AHB Buffers 38.6.3.4 Transmit AHB Buffers 38.6.3.5 DMA Bursting on the AHB 38.6.3.6 DMA Packet Buffer 38.6.3.7 Transmit Packet Buffer 38.6.3.8 Receive Packet Buffer 38.6.3.9 Priority Queueing in the DMA 38.6.4 MAC Transmit Block 38.6.5 MAC Receive Block 38.6.6 Checksum Offload for IP, TCP and UDP 38.6.6.1 Receiver Checksum Offload 38.6.6.2 Transmitter Checksum Offload 38.6.7 MAC Filtering Block 38.6.8 Broadcast Address 38.6.9 Hash Addressing 38.6.10 Copy all Frames (Promiscuous Mode) 38.6.11 Disable Copy of Pause Frames 38.6.12 VLAN Support 38.6.13 Wake on LAN Support 38.6.14 IEEE 1588 Support 38.6.15 Time Stamp Unit 38.6.16 MAC 802.3 Pause Frame Support 38.6.16.1 802.3 Pause Frame Reception 38.6.16.2 802.3 Pause Frame Transmission 38.6.17 MAC PFC Priority-based Pause Frame Support 38.6.17.1 PFC Pause Frame Reception 38.6.17.2 PFC Pause Frame Transmission 38.6.18 802.1Qav Support - Credit-based Shaping 38.6.19 PHY Interface 38.6.20 10/100 Operation 38.6.21 Jumbo Frames 38.7 Programming Interface 38.7.1 Initialization 38.7.1.1 Configuration 38.7.1.2 Receive Buffer List 38.7.1.3 Transmit Buffer List 38.7.1.4 Address Matching 38.7.1.5 PHY Maintenance 38.7.1.6 Interrupts 38.7.1.7 Transmitting Frames 38.7.1.8 Receiving Frames 38.7.2 Statistics Registers 38.8 Ethernet MAC (GMAC) User Interface 38.8.1 GMAC Network Control Register 38.8.2 GMAC Network Configuration Register 38.8.3 GMAC Network Status Register 38.8.4 GMAC User Register 38.8.5 GMAC DMA Configuration Register 38.8.6 GMAC Transmit Status Register 38.8.7 GMAC Receive Buffer Queue Base Address Register 38.8.8 GMAC Transmit Buffer Queue Base Address Register 38.8.9 GMAC Receive Status Register 38.8.10 GMAC Interrupt Status Register 38.8.11 GMAC Interrupt Enable Register 38.8.12 GMAC Interrupt Disable Register 38.8.13 GMAC Interrupt Mask Register 38.8.14 GMAC PHY Maintenance Register 38.8.15 GMAC Receive Pause Quantum Register 38.8.16 GMAC Transmit Pause Quantum Register 38.8.17 GMAC TX Partial Store and Forward Register 38.8.18 GMAC RX Partial Store and Forward Register 38.8.19 GMAC RX Jumbo Frame Max Length Register 38.8.20 GMAC Hash Register Bottom 38.8.21 GMAC Hash Register Top 38.8.22 GMAC Specific Address 1 Bottom Register 38.8.23 GMAC Specific Address 1 Top Register 38.8.24 GMAC Specific Address 2 Bottom Register 38.8.25 GMAC Specific Address 2 Top Register 38.8.26 GMAC Specific Address 3 Bottom Register 38.8.27 GMAC Specific Address 3 Top Register 38.8.28 GMAC Specific Address 4 Bottom Register 38.8.29 GMAC Specific Address 4 Top Register 38.8.30 GMAC Type ID Match 1 Register 38.8.31 GMAC Type ID Match 2 Register 38.8.32 GMAC Type ID Match 3 Register 38.8.33 GMAC Type ID Match 4 Register 38.8.34 GMAC Wake on LAN Register 38.8.35 GMAC IPG Stretch Register 38.8.36 GMAC Stacked VLAN Register 38.8.37 GMAC Transmit PFC Pause Register 38.8.38 GMAC Specific Address 1 Mask Bottom Register 38.8.39 GMAC Specific Address Mask 1 Top Register 38.8.40 GMAC 1588 Timer Nanosecond Comparison Register 38.8.41 GMAC 1588 Timer Second Comparison Low Register 38.8.42 GMAC 1588 Timer Second Comparison High Register 38.8.43 GMAC PTP Event Frame Transmitted Seconds High Register 38.8.44 GMAC PTP Event Frame Received Seconds High Register 38.8.45 GMAC PTP Peer Event Frame Transmitted Seconds High Register 38.8.46 GMAC PTP Peer Event Frame Received Seconds High Register 38.8.47 GMAC Octets Transmitted Low Register 38.8.48 GMAC Octets Transmitted High Register 38.8.49 GMAC Frames Transmitted Register 38.8.50 GMAC Broadcast Frames Transmitted Register 38.8.51 GMAC Multicast Frames Transmitted Register 38.8.52 GMAC Pause Frames Transmitted Register 38.8.53 GMAC 64 Byte Frames Transmitted Register 38.8.54 GMAC 65 to 127 Byte Frames Transmitted Register 38.8.55 GMAC 128 to 255 Byte Frames Transmitted Register 38.8.56 GMAC 256 to 511 Byte Frames Transmitted Register 38.8.57 GMAC 512 to 1023 Byte Frames Transmitted Register 38.8.58 GMAC 1024 to 1518 Byte Frames Transmitted Register 38.8.59 GMAC Greater Than 1518 Byte Frames Transmitted Register 38.8.60 GMAC Transmit Underruns Register 38.8.61 GMAC Single Collision Frames Register 38.8.62 GMAC Multiple Collision Frames Register 38.8.63 GMAC Excessive Collisions Register 38.8.64 GMAC Late Collisions Register 38.8.65 GMAC Deferred Transmission Frames Register 38.8.66 GMAC Carrier Sense Errors Register 38.8.67 GMAC Octets Received Low Register 38.8.68 GMAC Octets Received High Register 38.8.69 GMAC Frames Received Register 38.8.70 GMAC Broadcast Frames Received Register 38.8.71 GMAC Multicast Frames Received Register 38.8.72 GMAC Pause Frames Received Register 38.8.73 GMAC 64 Byte Frames Received Register 38.8.74 GMAC 65 to 127 Byte Frames Received Register 38.8.75 GMAC 128 to 255 Byte Frames Received Register 38.8.76 GMAC 256 to 511 Byte Frames Received Register 38.8.77 GMAC 512 to 1023 Byte Frames Received Register 38.8.78 GMAC 1024 to 1518 Byte Frames Received Register 38.8.79 GMAC 1519 to Maximum Byte Frames Received Register 38.8.80 GMAC Undersized Frames Received Register 38.8.81 GMAC Oversized Frames Received Register 38.8.82 GMAC Jabbers Received Register 38.8.83 GMAC Frame Check Sequence Errors Register 38.8.84 GMAC Length Field Frame Errors Register 38.8.85 GMAC Receive Symbol Errors Register 38.8.86 GMAC Alignment Errors Register 38.8.87 GMAC Receive Resource Errors Register 38.8.88 GMAC Receive Overruns Register 38.8.89 GMAC IP Header Checksum Errors Register 38.8.90 GMAC TCP Checksum Errors Register 38.8.91 GMAC UDP Checksum Errors Register 38.8.92 GMAC 1588 Timer Increment Sub-nanoseconds Register 38.8.93 GMAC 1588 Timer Seconds High Register 38.8.94 GMAC 1588 Timer Seconds Low Register 38.8.95 GMAC 1588 Timer Nanoseconds Register 38.8.96 GMAC 1588 Timer Adjust Register 38.8.97 GMAC 1588 Timer Increment Register 38.8.98 GMAC PTP Event Frame Transmitted Seconds Low Register 38.8.99 GMAC PTP Event Frame Transmitted Nanoseconds Register 38.8.100 GMAC PTP Event Frame Received Seconds Low Register 38.8.101 GMAC PTP Event Frame Received Nanoseconds Register 38.8.102 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 38.8.103 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 38.8.104 GMAC PTP Peer Event Frame Received Seconds Low Register 38.8.105 GMAC PTP Peer Event Frame Received Nanoseconds Register 38.8.106 GMAC Interrupt Status Register Priority Queue x 38.8.107 GMAC Transmit Buffer Queue Base Address Register Priority Queue x 38.8.108 GMAC Receive Buffer Queue Base Address Register Priority Queue x 38.8.109 GMAC Receive Buffer Size Register Priority Queue x 38.8.110 GMAC Credit-Based Shaping Control Register 38.8.111 GMAC Credit-Based Shaping IdleSlope Register for Queue A 38.8.112 GMAC Credit-Based Shaping IdleSlope Register for Queue B 38.8.113 GMAC Screening Type 1 Register x Priority Queue 38.8.114 GMAC Screening Type 2 Register x Priority Queue 38.8.115 GMAC Interrupt Enable Register Priority Queue x 38.8.116 GMAC Interrupt Disable Register Priority Queue x 38.8.117 GMAC Interrupt Mask Register Priority Queue x 38.8.118 GMAC Screening Type 2 EtherType Register x 38.8.119 GMAC Screening Type 2 Compare Word 0 Register x 38.8.120 GMAC Screening Type 2 Compare Word 1 Register x 39. High Speed Multimedia Card Interface (HSMCI) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 Application Block Diagram 39.5 Pin Name List 39.6 Product Dependencies 39.6.1 I/O Lines 39.6.2 Power Management 39.6.3 Interrupt Sources 39.7 Bus Topology 39.8 High Speed MultiMedia Card Operations 39.8.1 Command - Response Operation 39.8.2 Data Transfer Operation 39.8.3 Read Operation 39.8.4 Write Operation 39.8.5 WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller 39.8.6 READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller 39.9 SD/SDIO Card Operation 39.9.1 SDIO Data Transfer Type 39.9.2 SDIO Interrupts 39.10 CE-ATA Operation 39.10.1 Executing an ATA Polling Command 39.10.2 Executing an ATA Interrupt Command 39.10.3 Aborting an ATA Command 39.10.4 CE-ATA Error Recovery 39.11 HSMCI Boot Operation Mode 39.11.1 Boot Procedure, Processor Mode 39.11.2 Boot Procedure DMA Mode 39.12 HSMCI Transfer Done Timings 39.12.1 Definition 39.12.2 Read Access 39.12.3 Write Access 39.13 Register Write Protection 39.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 39.14.1 HSMCI Control Register 39.14.2 HSMCI Mode Register 39.14.3 HSMCI Data Timeout Register 39.14.4 HSMCI SDCard/SDIO Register 39.14.5 HSMCI Argument Register 39.14.6 HSMCI Command Register 39.14.7 HSMCI Block Register 39.14.8 HSMCI Completion Signal Timeout Register 39.14.9 HSMCI Response Register 39.14.10 HSMCI Receive Data Register 39.14.11 HSMCI Transmit Data Register 39.14.12 HSMCI Status Register 39.14.13 HSMCI Interrupt Enable Register 39.14.14 HSMCI Interrupt Disable Register 39.14.15 HSMCI Interrupt Mask Register 39.14.16 HSMCI DMA Configuration Register 39.14.17 HSMCI Configuration Register 39.14.18 HSMCI Write Protection Mode Register 39.14.19 HSMCI Write Protection Status Register 39.14.20 HSMCI FIFOx Memory Aperture 40. Serial Peripheral Interface (SPI) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Application Block Diagram 40.5 Signal Description 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt 40.6.4 Direct Memory Access Controller (DMAC) 40.7 Functional Description 40.7.1 Modes of Operation 40.7.2 Data Transfer 40.7.3 Master Mode Operations 40.7.3.1 Master Mode Block Diagram 40.7.3.2 Master Mode Flow Diagram 40.7.3.3 Clock Generation 40.7.3.4 Transfer Delays 40.7.3.5 Peripheral Selection 40.7.3.6 SPI Direct Access Memory Controller (DMAC) 40.7.3.7 Peripheral Chip Select Decoding 40.7.3.8 Peripheral Deselection without DMA 40.7.3.9 Peripheral Deselection with DMA 40.7.3.10 Mode Fault Detection 40.7.4 SPI Slave Mode 40.7.5 Register Write Protection 40.8 Serial Peripheral Interface (SPI) User Interface 40.8.1 SPI Control Register 40.8.2 SPI Mode Register 40.8.3 SPI Receive Data Register 40.8.4 SPI Transmit Data Register 40.8.5 SPI Status Register 40.8.6 SPI Interrupt Enable Register 40.8.7 SPI Interrupt Disable Register 40.8.8 SPI Interrupt Mask Register 40.8.9 SPI Chip Select Register 40.8.10 SPI Write Protection Mode Register 40.8.11 SPI Write Protection Status Register 41. Quad SPI Interface (QSPI) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Signal Description 41.5 Product Dependencies 41.5.1 I/O Lines 41.5.2 Power Management 41.5.3 Interrupt Sources 41.5.4 Direct Memory Access Controller (DMA) 41.6 Functional Description 41.6.1 Serial Clock Baud Rate 41.6.2 Serial Clock Phase and Polarity 41.6.3 Transfer Delays 41.6.4 QSPI SPI Mode 41.6.4.1 SPI Mode Operations 41.6.4.2 SPI Mode Block Diagram 41.6.4.3 SPI Mode Flow Diagram 41.6.4.4 Peripheral Deselection without DMA 41.6.4.5 Peripheral Deselection with DMA 41.6.5 QSPI Serial Memory Mode 41.6.5.1 Instruction Frame 41.6.5.2 Instruction Frame Transmission 41.6.5.3 Read Memory Transfer 41.6.5.4 Continuous Read Mode 41.6.5.5 Instruction Frame Transmission Examples 41.6.6 Scrambling/Unscrambling Function 41.6.7 Register Write Protection 41.7 Quad SPI Interface (QSPI) User Interface 41.7.1 QSPI Control Register 41.7.2 QSPI Mode Register 41.7.3 QSPI Receive Data Register 41.7.4 QSPI Transmit Data Register 41.7.5 QSPI Status Register 41.7.6 QSPI Interrupt Enable Register 41.7.7 QSPI Interrupt Disable Register 41.7.8 QSPI Interrupt Mask Register 41.7.9 QSPI Serial Clock Register 41.7.10 QSPI Instruction Address Register 41.7.11 QSPI Instruction Code Register 41.7.12 QSPI Instruction Frame Register 41.7.13 QSPI Scrambling Mode Register 41.7.14 QSPI Scrambling Key Register 41.7.15 QSPI Write Protection Mode Register 41.7.16 QSPI Write Protection Status Register 42. Two-wire Interface (TWIHS) 42.1 Description 42.2 Embedded Characteristics 42.3 List of Abbreviations 42.4 Block Diagram 42.4.1 I/O Lines Description 42.5 Product Dependencies 42.5.1 I/O Lines 42.5.2 Power Management 42.5.3 Interrupt Sources 42.6 Functional Description 42.6.1 Transfer Format 42.6.2 Modes of Operation 42.6.3 Master Mode 42.6.3.1 Definition 42.6.3.2 Programming Master Mode 42.6.3.3 Transfer Rate Clock Source 42.6.3.4 Master Transmitter Mode 42.6.3.5 Master Receiver Mode 42.6.3.6 Internal Address 7-bit Slave Addressing 10-bit Slave Addressing 42.6.3.7 Repeated Start 42.6.3.8 Bus Clear Command 42.6.3.9 Using the DMA Controller (DMAC) in Master Mode Data Transmit with the DMA in Master Mode Data Receive with the DMA in Master Mode 42.6.3.10 SMBus Mode Packet Error Checking Timeouts 42.6.3.11 SMBus Quick Command (Master Mode Only) 42.6.3.12 Read/Write Flowcharts 42.6.4 Multi-master Mode 42.6.4.1 Definition 42.6.4.2 Different Multi-master Modes TWIHS as Master Only TWIHS as Master or Slave 42.6.5 Slave Mode 42.6.5.1 Definition 42.6.5.2 Programming Slave Mode 42.6.5.3 Receiving Data Read Sequence Write Sequence Clock Stretching Sequence General Call 42.6.5.4 Data Transfer Read Operation Write Operation General Call Clock Stretching Clock Stretching in Read Mode Clock Stretching in Write Mode Reversal after a Repeated Start Reversal of Read to Write Reversal of Write to Read 42.6.5.5 Using the DMA Controller (DMAC) in Slave Mode Data Transmit with the DMA in Slave Mode Data Receive with the DMA in Slave Mode 42.6.5.6 SMBus Mode Packet Error Checking Timeouts 42.6.5.7 High-Speed Slave Mode Read/Write Operation Usage 42.6.5.8 Asynchronous Partial Wake-up (SleepWalking) 42.6.5.9 Slave Read Write Flowcharts 42.6.6 TWIHS Comparison Function on Received Character 42.6.7 Register Write Protection 42.7 Two-wire Interface High Speed (TWIHS) User Interface 42.7.1 TWIHS Control Register 42.7.2 TWIHS Master Mode Register 42.7.3 TWIHS Slave Mode Register 42.7.4 TWIHS Internal Address Register 42.7.5 TWIHS Clock Waveform Generator Register 42.7.6 TWIHS Status Register 42.7.7 TWIHS SMBus Timing Register 42.7.8 TWIHS Filter Register 42.7.9 TWIHS Interrupt Enable Register 42.7.10 TWIHS Interrupt Disable Register 42.7.11 TWIHS Interrupt Mask Register 42.7.12 TWIHS Receive Holding Register 42.7.13 TWIHS SleepWalking Matching Register 42.7.14 TWIHS Transmit Holding Register 42.7.15 TWIHS Write Protection Mode Register 42.7.16 TWIHS Write Protection Status Register 43. Synchronous Serial Controller (SSC) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Application Block Diagram 43.5 SSC Application Examples 43.6 Pin Name List 43.7 Product Dependencies 43.7.1 I/O Lines 43.7.2 Power Management 43.7.3 Interrupt 43.8 Functional Description 43.8.1 Clock Management 43.8.1.1 Clock Divider 43.8.1.2 Transmitter Clock Management 43.8.1.3 Receiver Clock Management 43.8.1.4 Serial Clock Ratio Considerations 43.8.2 Transmitter Operations 43.8.3 Receiver Operations 43.8.4 Start 43.8.5 Frame Sync 43.8.5.1 Frame Sync Data 43.8.5.2 Frame Sync Edge Detection 43.8.6 Receive Compare Modes 43.8.6.1 Compare Functions 43.8.7 Data Format 43.8.8 Loop Mode 43.8.9 Interrupt 43.8.10 Register Write Protection 43.9 Synchronous Serial Controller (SSC) User Interface 43.9.1 SSC Control Register 43.9.2 SSC Clock Mode Register 43.9.3 SSC Receive Clock Mode Register 43.9.4 SSC Receive Frame Mode Register 43.9.5 SSC Transmit Clock Mode Register 43.9.6 SSC Transmit Frame Mode Register 43.9.7 SSC Receive Holding Register 43.9.8 SSC Transmit Holding Register 43.9.9 SSC Receive Synchronization Holding Register 43.9.10 SSC Transmit Synchronization Holding Register 43.9.11 SSC Receive Compare 0 Register 43.9.12 SSC Receive Compare 1 Register 43.9.13 SSC Status Register 43.9.14 SSC Interrupt Enable Register 43.9.15 SSC Interrupt Disable Register 43.9.16 SSC Interrupt Mask Register 43.9.17 SSC Write Protection Mode Register 43.9.18 SSC Write Protection Status Register 44. Inter-IC Sound Controller (I2SC) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 I/O Lines Description 44.5 Product Dependencies 44.5.1 I/O Lines 44.5.2 Power Management 44.5.3 Clocks 44.5.4 DMA Controller 44.5.5 Interrupt Sources 44.6 Functional Description 44.6.1 Initialization 44.6.2 Basic Operation 44.6.3 Master, Controller and Slave Modes 44.6.4 I2S Reception and Transmission Sequence 44.6.5 Serial Clock and Word Select Generation 44.6.6 Mono 44.6.7 Holding Registers 44.6.8 DMA Controller Operation 44.6.9 Loop-back Mode 44.6.10 Interrupts 44.7 I2SC Application Examples 44.8 Inter-IC Sound Controller (I2SC) User Interface 44.8.1 Inter-IC Sound Controller Control Register 44.8.2 Inter-IC Sound Controller Mode Register 44.8.3 Inter-IC Sound Controller Status Register 44.8.4 Inter-IC Sound Controller Status Clear Register 44.8.5 Inter-IC Sound Controller Status Set Register 44.8.6 Inter-IC Sound Controller Interrupt Enable Register 44.8.7 Inter-IC Sound Controller Interrupt Disable Register 44.8.8 Inter-IC Sound Controller Interrupt Mask Register 44.8.9 Inter-IC Sound Controller Receiver Holding Register 44.8.10 Inter-IC Sound Controller Transmitter Holding Register 45. Universal Synchronous Asynchronous Receiver Transceiver (USART) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 I/O Lines Description 45.5 Product Dependencies 45.5.1 I/O Lines 45.5.2 Power Management 45.5.3 Interrupt Sources 45.6 Functional Description 45.6.1 Baud Rate Generator 45.6.1.1 Baud Rate in Asynchronous Mode Baud Rate Calculation Example 45.6.1.2 Fractional Baud Rate in Asynchronous Mode 45.6.1.3 Baud Rate in Synchronous Mode or SPI Mode 45.6.1.4 Baud Rate in ISO 7816 Mode 45.6.2 Receiver and Transmitter Control 45.6.3 Synchronous and Asynchronous Modes 45.6.3.1 Transmitter Operations 45.6.3.2 Manchester Encoder Drift Compensation 45.6.3.3 Asynchronous Receiver 45.6.3.4 Manchester Decoder 45.6.3.5 Radio Interface: Manchester Encoded USART Application 45.6.3.6 Synchronous Receiver 45.6.3.7 Receiver Operations 45.6.3.8 Parity 45.6.3.9 Multidrop Mode 45.6.3.10 Transmitter Timeguard 45.6.3.11 Receiver Time-out 45.6.3.12 Framing Error 45.6.3.13 Transmit Break 45.6.3.14 Receive Break 45.6.3.15 Hardware Handshaking 45.6.4 ISO7816 Mode 45.6.4.1 ISO7816 Mode Overview 45.6.4.2 Protocol T = 0 Receive Error Counter Receive NACK Inhibit Transmit Character Repetition Disable Successive Receive NACK 45.6.4.3 Protocol T = 1 45.6.5 IrDA Mode 45.6.5.1 IrDA Modulation 45.6.5.2 IrDA Baud Rate 45.6.5.3 IrDA Demodulator 45.6.6 RS485 Mode 45.6.7 Modem Mode 45.6.8 SPI Mode 45.6.8.1 Modes of Operation 45.6.8.2 Baud Rate 45.6.8.3 Data Transfer 45.6.8.4 Receiver and Transmitter Control 45.6.8.5 Character Transmission 45.6.8.6 Character Reception 45.6.8.7 Receiver Timeout 45.6.9 LIN Mode 45.6.9.1 Modes of Operation 45.6.9.2 Baud Rate Configuration 45.6.9.3 Receiver and Transmitter Control 45.6.9.4 Character Transmission 45.6.9.5 Character Reception 45.6.9.6 Header Transmission (Master Node Configuration) 45.6.9.7 Header Reception (Slave Node Configuration) 45.6.9.8 Slave Node Synchronization 45.6.9.9 Identifier Parity 45.6.9.10 Node Action 45.6.9.11 Response Data Length 45.6.9.12 Checksum 45.6.9.13 Frame Slot Mode 45.6.9.14 LIN Errors Bit Error Inconsistent Synch Field Error Identifier Parity Error Checksum Error Slave Not Responding Error Synch Tolerance Error Header Timeout Error 45.6.9.15 LIN Frame Handling Master Node Configuration Slave Node Configuration 45.6.9.16 LIN Frame Handling with the DMAC Master Node Configuration Slave Node Configuration 45.6.9.17 Wake-up Request 45.6.9.18 Bus Idle Time-out 45.6.10 LON Mode 45.6.10.1 Mode of Operation 45.6.10.2 Receiver and Transmitter Control 45.6.10.3 Character Transmission 45.6.10.4 Character Reception 45.6.10.5 LON Frame Encoding / Decoding Preamble Transmission Preamble Reception Header Transmission Header Reception Data CRC End Of Frame 45.6.10.6 LON Operating Modes Transmitting/Receiving Modules comm_type Collision Detection Collision Detection Mode. Collision Detection After CRC Random Number Generation 45.6.10.7 LON Node Backlog Estimation Optional Collision Detection Feature And Backlog Estimation 45.6.10.8 LON Timings Beta2 Beta1 Tx/Rx Pcycle Timer Wbase Priority Slots Indeterminate Time End of Frame Condition 45.6.10.9 LON Errors Underrun Error Collision Detection LON Frame Early Termination Reception Error Backlog Overflow 45.6.10.10 Drift Compensation 45.6.10.11 LON Frame Handling Sending A Frame Receiving A Frame 45.6.10.12 LON Frame Handling with the Peripheral DMA Controller Configuration DMA and Collision Detection 45.6.11 Test Modes 45.6.11.1 Normal Mode 45.6.11.2 Automatic Echo Mode 45.6.11.3 Local Loopback Mode 45.6.11.4 Remote Loopback Mode 45.6.12 Register Write Protection 45.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 45.7.1 USART Control Register 45.7.2 USART Control Register (SPI_MODE) 45.7.3 USART Mode Register 45.7.4 USART Mode Register (SPI_MODE) 45.7.5 USART Interrupt Enable Register 45.7.6 USART Interrupt Enable Register (SPI_MODE) 45.7.7 USART Interrupt Enable Register (LIN_MODE) 45.7.8 USART Interrupt Enable Register (LON_MODE) 45.7.9 USART Interrupt Disable Register 45.7.10 USART Interrupt Disable Register (SPI_MODE) 45.7.11 USART Interrupt Disable Register (LIN_MODE) 45.7.12 USART Interrupt Disable Register (LON_MODE) 45.7.13 USART Interrupt Mask Register 45.7.14 USART Interrupt Mask Register (SPI_MODE) 45.7.15 USART Interrupt Mask Register (LIN_MODE) 45.7.16 USART Interrupt Mask Register (LON_MODE) 45.7.17 USART Channel Status Register 45.7.18 USART Channel Status Register (SPI_MODE) 45.7.19 USART Channel Status Register (LIN_MODE) 45.7.20 USART Channel Status Register (LON_MODE) 45.7.21 USART Receive Holding Register 45.7.22 USART Transmit Holding Register 45.7.23 USART Baud Rate Generator Register 45.7.24 USART Receiver Time-out Register 45.7.25 USART Transmitter Timeguard Register 45.7.26 USART Transmitter Timeguard Register (LON_MODE) 45.7.27 USART FI DI RATIO Register 45.7.28 USART FI DI RATIO Register (LON_MODE) 45.7.29 USART Number of Errors Register 45.7.30 USART IrDA Filter Register 45.7.31 USART Manchester Configuration Register 45.7.32 USART LIN Mode Register 45.7.33 USART LIN Identifier Register 45.7.34 USART LIN Baud Rate Register 45.7.35 USART LON Mode Register 45.7.36 USART LON Preamble Register 45.7.37 USART LON Data Length Register 45.7.38 USART LON L2HDR Register 45.7.39 USART LON Backlog Register 45.7.40 USART LON Beta1 Tx Register 45.7.41 USART LON Beta1 Rx Register 45.7.42 USART LON Priority Register 45.7.43 USART LON IDT Tx Register 45.7.44 USART LON IDT Rx Register 45.7.45 USART IC DIFF Register 45.7.46 USART Write Protection Mode Register 45.7.47 USART Write Protection Status Register 46. Universal Asynchronous Receiver Transmitter (UART) 46.1 Description 46.2 Embedded Characteristics 46.3 Block Diagram 46.4 Product Dependencies 46.4.1 I/O Lines 46.4.2 Power Management 46.4.3 Interrupt Sources 46.5 Functional Description 46.5.1 Baud Rate Generator 46.5.2 Receiver 46.5.2.1 Receiver Reset, Enable and Disable 46.5.2.2 Start Detection and Data Sampling 46.5.2.3 Receiver Ready 46.5.2.4 Receiver Overrun 46.5.2.5 Parity Error 46.5.2.6 Receiver Framing Error 46.5.2.7 Receiver Digital Filter 46.5.3 Transmitter 46.5.3.1 Transmitter Reset, Enable and Disable 46.5.3.2 Transmit Format 46.5.3.3 Transmitter Control 46.5.4 DMA Support 46.5.5 Comparison Function on Received Character 46.5.6 Asynchronous and Partial Wake-up (SleepWalking) 46.5.7 Register Write Protection 46.5.8 Test Modes 46.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 46.6.1 UART Control Register 46.6.2 UART Mode Register 46.6.3 UART Interrupt Enable Register 46.6.4 UART Interrupt Disable Register 46.6.5 UART Interrupt Mask Register 46.6.6 UART Status Register 46.6.7 UART Receiver Holding Register 46.6.8 UART Transmit Holding Register 46.6.9 UART Baud Rate Generator Register 46.6.10 UART Comparison Register 46.6.11 UART Write Protection Mode Register 47. Controller Area Network (MCAN) 47.1 Description 47.2 Embedded Characteristics 47.3 Block Diagram 47.4 Product Dependencies 47.4.1 I/O Lines 47.4.2 Power Management 47.4.3 Interrupt Sources 47.4.4 Address Configuration 47.5 Functional Description 47.5.1 Operating Modes 47.5.1.1 Software Initialization 47.5.1.2 Normal Operation 47.5.1.3 CAN FD Operation 47.5.1.4 Transceiver Delay Compensation Description Configuration and Status 47.5.1.5 Restricted Operation Mode 47.5.1.6 Bus Monitoring Mode 47.5.1.7 Disabled Automatic Retransmission Frame Transmission in DAR Mode 47.5.1.8 Power Down (Sleep Mode) 47.5.1.9 Test Modes External Loop Back Mode Internal Loop Back Mode 47.5.2 Timestamp Generation 47.5.3 Timeout Counter 47.5.4 Rx Handling 47.5.4.1 Acceptance Filtering Range Filter Filter for Specific IDs Classic Bit Mask Filter Standard Message ID Filtering Extended Message ID Filtering 47.5.4.2 Rx FIFOs Rx FIFO Blocking Mode Rx FIFO Overwrite Mode 47.5.4.3 Dedicated Rx Buffers Rx Buffer Handling 47.5.4.4 Debug on CAN Support Filtering for Debug Messages Debug Message Handling 47.5.5 Tx Handling 47.5.5.1 Transmit Pause 47.5.5.2 Dedicated Tx Buffers 47.5.5.3 Tx FIFO 47.5.5.4 Tx Queue 47.5.5.5 Mixed Dedicated Tx Buffers / Tx FIFO 47.5.5.6 Mixed Dedicated Tx Buffers / Tx Queue 47.5.5.7 Transmit Cancellation 47.5.5.8 Tx Event Handling 47.5.6 FIFO Acknowledge Handling 47.5.7 Message RAM 47.5.7.1 Message RAM Configuration 47.5.7.2 Rx Buffer and FIFO Element 47.5.7.3 Tx Buffer Element 47.5.7.4 Tx Event FIFO Element 47.5.7.5 Standard Message ID Filter Element 47.5.7.6 Extended Message ID Filter Element 47.5.8 Hardware Reset Description 47.6 Controller Area Network (MCAN) User Interface 47.6.1 MCAN Core Release Register 47.6.2 MCAN Endian Register 47.6.3 MCAN Customer Register 47.6.4 MCAN Fast Bit Timing and Prescaler Register 47.6.5 MCAN Test Register 47.6.6 MCAN RAM Watchdog Register 47.6.7 MCAN CC Control Register 47.6.8 MCAN Bit Timing and Prescaler Register 47.6.9 MCAN Timestamp Counter Configuration Register 47.6.10 MCAN Timestamp Counter Value Register 47.6.11 MCAN Timeout Counter Configuration Register 47.6.12 MCAN Timeout Counter Value Register 47.6.13 MCAN Error Counter Register 47.6.14 MCAN Protocol Status Register 47.6.15 MCAN Interrupt Register 47.6.16 MCAN Interrupt Enable Register 47.6.17 MCAN Interrupt Line Select Register 47.6.18 MCAN Interrupt Line Enable 47.6.19 MCAN Global Filter Configuration 47.6.20 MCAN Standard ID Filter Configuration 47.6.21 MCAN Extended ID Filter Configuration 47.6.22 MCAN Extended ID AND Mask 47.6.23 MCAN High Priority Message Status 47.6.24 MCAN New Data 1 47.6.25 MCAN New Data 2 47.6.26 MCAN Receive FIFO 0 Configuration 47.6.27 MCAN Receive FIFO 0 Status 47.6.28 MCAN Receive FIFO 0 Acknowledge 47.6.29 MCAN Receive Buffer Configuration 47.6.30 MCAN Receive FIFO 1 Configuration 47.6.31 MCAN Receive FIFO 1 Status 47.6.32 MCAN Receive FIFO 1 Acknowledge 47.6.33 MCAN Receive Buffer / FIFO Element Size Configuration 47.6.34 MCAN Tx Buffer Configuration 47.6.35 MCAN Tx FIFO/Queue Status 47.6.36 MCAN Tx Buffer Element Size Configuration 47.6.37 MCAN Transmit Buffer Request Pending 47.6.38 MCAN Transmit Buffer Add Request 47.6.39 MCAN Transmit Buffer Cancellation Request 47.6.40 MCAN Transmit Buffer Transmission Occurred 47.6.41 MCAN Transmit Buffer Cancellation Finished 47.6.42 MCAN Transmit Buffer Transmission Interrupt Enable 47.6.43 MCAN Transmit Buffer Cancellation Finished Interrupt Enable 47.6.44 MCAN Transmit Event FIFO Configuration 47.6.45 MCAN Tx Event FIFO Status 47.6.46 MCAN Tx Event FIFO Acknowledge 48. Timer Counter (TC) 48.1 Description 48.2 Embedded Characteristics 48.3 Block Diagram 48.4 Pin List 48.5 Product Dependencies 48.5.1 I/O Lines 48.5.2 Power Management 48.5.3 Interrupt Sources 48.5.4 Synchronization Inputs from PWM 48.5.5 Fault Output 48.6 Functional Description 48.6.1 Description 48.6.2 16-bit Counter 48.6.3 Clock Selection 48.6.4 Clock Control 48.6.5 Operating Modes 48.6.6 Trigger 48.6.7 Capture Mode 48.6.8 Capture Registers A and B 48.6.9 Transfer with DMAC 48.6.10 Trigger Conditions 48.6.11 Waveform Mode 48.6.12 Waveform Selection 48.6.12.1 WAVSEL = 00 48.6.12.2 WAVSEL = 10 48.6.12.3 WAVSEL = 01 48.6.12.4 WAVSEL = 11 48.6.13 External Event/Trigger Conditions 48.6.14 Synchronization with PWM 48.6.15 Output Controller 48.6.16 Quadrature Decoder 48.6.16.1 Description 48.6.16.2 Input Pre-processing 48.6.16.3 Direction Status and Change Detection 48.6.16.4 Position and Rotation Measurement 48.6.16.5 Speed Measurement 48.6.17 2-bit Gray Up/Down Counter for Stepper Motor 48.6.18 Fault Mode 48.6.19 Register Write Protection 48.7 Timer Counter (TC) User Interface 48.7.1 TC Channel Control Register 48.7.2 TC Channel Mode Register: Capture Mode 48.7.3 TC Channel Mode Register: Waveform Mode 48.7.4 TC Stepper Motor Mode Register 48.7.5 TC Register AB 48.7.6 TC Counter Value Register 48.7.7 TC Register A 48.7.8 TC Register B 48.7.9 TC Register C 48.7.10 TC Status Register 48.7.11 TC Interrupt Enable Register 48.7.12 TC Interrupt Disable Register 48.7.13 TC Interrupt Mask Register 48.7.14 TC Extended Mode Register 48.7.15 TC Block Control Register 48.7.16 TC Block Mode Register 48.7.17 TC QDEC Interrupt Enable Register 48.7.18 TC QDEC Interrupt Disable Register 48.7.19 TC QDEC Interrupt Mask Register 48.7.20 TC QDEC Interrupt Status Register 48.7.21 TC Fault Mode Register 48.7.22 TC Write Protection Mode Register 49. Pulse Width Modulation Controller (PWM) 49.1 Description 49.2 Embedded Characteristics 49.3 Block Diagram 49.4 I/O Lines Description 49.5 Product Dependencies 49.5.1 I/O Lines 49.5.2 Power Management 49.5.3 Interrupt Sources 49.5.4 Fault Inputs 49.6 Functional Description 49.6.1 PWM Clock Generator 49.6.2 PWM Channel 49.6.2.1 Channel Block Diagram 49.6.2.2 Comparator 49.6.2.3 Trigger Selection for Timer Counter Delay Measurement Cumulated ON Time Measurement 49.6.2.4 2-bit Gray Up/Down Counter for Stepper Motor 49.6.2.5 Dead-Time Generator PWM Push-Pull Mode 49.6.2.6 Output Override 49.6.2.7 Fault Protection Recoverable Fault 49.6.2.8 Spread Spectrum Counter 49.6.2.9 Synchronous Channels Method 1: Manual write of duty-cycle values and manual trigger of the update Method 2: Manual write of duty-cycle values and automatic trigger of the update Method 3: Automatic write of duty-cycle values and automatic trigger of the update 49.6.2.10 Update Time for Double-Buffering Registers 49.6.3 PWM Comparison Units 49.6.4 PWM Event Lines 49.6.5 PWM External Trigger Mode 49.6.5.1 External PWM Reset Mode Application Example 49.6.5.2 External PWM Start Mode Application Example 49.6.5.3 Cycle-By-Cycle Duty Mode Description Application Example 49.6.5.4 Leading-Edge Blanking (LEB) 49.6.6 PWM Controller Operations 49.6.6.1 Initialization 49.6.6.2 Source Clock Selection Criteria 49.6.6.3 Changing the Duty-Cycle, the Period and the Dead-Times 49.6.6.4 Changing the Update Period of Synchronous Channels 49.6.6.5 Changing the Comparison Value and the Comparison Configuration 49.6.6.6 Interrupt Sources 49.6.7 Register Write Protection 49.7 Pulse Width Modulation Controller (PWM) User Interface 49.7.1 PWM Clock Register 49.7.2 PWM Enable Register 49.7.3 PWM Disable Register 49.7.4 PWM Status Register 49.7.5 PWM Interrupt Enable Register 1 49.7.6 PWM Interrupt Disable Register 1 49.7.7 PWM Interrupt Mask Register 1 49.7.8 PWM Interrupt Status Register 1 49.7.9 PWM Sync Channels Mode Register 49.7.10 PWM DMA Register 49.7.11 PWM Sync Channels Update Control Register 49.7.12 PWM Sync Channels Update Period Register 49.7.13 PWM Sync Channels Update Period Update Register 49.7.14 PWM Interrupt Enable Register 2 49.7.15 PWM Interrupt Disable Register 2 49.7.16 PWM Interrupt Mask Register 2 49.7.17 PWM Interrupt Status Register 2 49.7.18 PWM Output Override Value Register 49.7.19 PWM Output Selection Register 49.7.20 PWM Output Selection Set Register 49.7.21 PWM Output Selection Clear Register 49.7.22 PWM Output Selection Set Update Register 49.7.23 PWM Output Selection Clear Update Register 49.7.24 PWM Fault Mode Register 49.7.25 PWM Fault Status Register 49.7.26 PWM Fault Clear Register 49.7.27 PWM Fault Protection Value Register 1 49.7.28 PWM Fault Protection Enable Register 49.7.29 PWM Event Line x Register 49.7.30 PWM Spread Spectrum Register 49.7.31 PWM Spread Spectrum Update Register 49.7.32 PWM Stepper Motor Mode Register 49.7.33 PWM Fault Protection Value Register 2 49.7.34 PWM Write Protection Control Register 49.7.35 PWM Write Protection Status Register 49.7.36 PWM Comparison x Value Register 49.7.37 PWM Comparison x Value Update Register 49.7.38 PWM Comparison x Mode Register 49.7.39 PWM Comparison x Mode Update Register 49.7.40 PWM Channel Mode Register 49.7.41 PWM Channel Duty Cycle Register 49.7.42 PWM Channel Duty Cycle Update Register 49.7.43 PWM Channel Period Register 49.7.44 PWM Channel Period Update Register 49.7.45 PWM Channel Counter Register 49.7.46 PWM Channel Dead Time Register 49.7.47 PWM Channel Dead Time Update Register 49.7.48 PWM Channel Mode Update Register 49.7.49 PWM External Trigger Register 49.7.50 PWM Leading-Edge Blanking Register 50. Analog Front-End Controller (AFEC) 50.1 Description 50.2 Embedded Characteristics 50.3 Block Diagram 50.4 Signal Description 50.5 Product Dependencies 50.5.1 I/O Lines 50.5.2 Power Management 50.5.3 Interrupt Sources 50.5.4 Temperature Sensor 50.5.5 Timer Triggers 50.5.6 PWM Event Line 50.5.7 Fault Output 50.5.8 Conversion Performances 50.6 Functional Description 50.6.1 Analog Front-End Conversion 50.6.2 Conversion Reference 50.6.3 Conversion Resolution 50.6.4 Conversion Results 50.6.5 Conversion Results Format 50.6.6 Conversion Triggers 50.6.7 Sleep Mode and Conversion Sequencer 50.6.8 Comparison Window 50.6.9 Differential Inputs 50.6.10 Sample-and-Hold Modes 50.6.11 Input Gain and Offset 50.6.12 AFE Timings 50.6.13 Temperature Sensor 50.6.14 Enhanced Resolution Mode and Digital Averaging Function 50.6.15 Automatic Error Correction 50.6.16 Buffer Structure 50.6.17 Fault Output 50.6.18 Register Write Protection 50.7 Analog Front-End Controller (AFEC) User Interface 50.7.1 AFEC Control Register 50.7.2 AFEC Mode Register 50.7.3 AFEC Extended Mode Register 50.7.4 AFEC Channel Sequence 1 Register 50.7.5 AFEC Channel Sequence 2 Register 50.7.6 AFEC Channel Enable Register 50.7.7 AFEC Channel Disable Register 50.7.8 AFEC Channel Status Register 50.7.9 AFEC Last Converted Data Register 50.7.10 AFEC Interrupt Enable Register 50.7.11 AFEC Interrupt Disable Register 50.7.12 AFEC Interrupt Mask Register 50.7.13 AFEC Interrupt Status Register 50.7.14 AFEC Overrun Status Register 50.7.15 AFEC Compare Window Register 50.7.16 AFEC Channel Gain Register 50.7.17 AFEC Channel Differential Register 50.7.18 AFEC Channel Selection Register 50.7.19 AFEC Channel Data Register 50.7.20 AFEC Channel Offset Compensation Register 50.7.21 AFEC Temperature Sensor Mode Register 50.7.22 AFEC Temperature Compare Window Register 50.7.23 AFEC Analog Control Register 50.7.24 AFEC Sample & Hold Mode Register 50.7.25 AFEC Correction Select Register 50.7.26 AFEC Correction Values Register 50.7.27 AFEC Channel Error Correction Register 50.7.28 AFEC Write Protection Mode Register 50.7.29 AFEC Write Protection Status Register 51. Digital-to-Analog Converter Controller (DACC) 51.1 Description 51.2 Embedded Characteristics 51.3 Block Diagram 51.4 Signal Description 51.5 Product Dependencies 51.5.1 I/O Lines 51.5.2 Power Management 51.5.3 Interrupt Sources 51.5.4 Conversion Performances 51.6 Functional Description 51.6.1 Digital-to-Analog Conversion 51.6.2 Conversion Results 51.6.3 Analog Output Mode Selection 51.6.4 Conversion Modes 51.6.4.1 Trigger Mode 51.6.4.2 Free-Running Mode 51.6.4.3 Max Speed Mode 51.6.4.4 Bypass Mode 51.6.4.5 Interpolation Mode 51.6.5 Conversion FIFO 51.6.6 Register Write Protection 51.7 Digital-to-Analog Converter Controller (DACC) User Interface 51.7.1 DACC Control Register 51.7.2 DACC Mode Register 51.7.3 DACC Trigger Register 51.7.4 DACC Channel Enable Register 51.7.5 DACC Channel Disable Register 51.7.6 DACC Channel Status Register 51.7.7 DACC Conversion Data Register 51.7.8 DACC Interrupt Enable Register 51.7.9 DACC Interrupt Disable Register 51.7.10 DACC Interrupt Mask Register 51.7.11 DACC Interrupt Status Register 51.7.12 DACC Analog Current Register 51.7.13 DACC Write Protection Mode Register 51.7.14 DACC Write Protection Status Register 52. Analog Comparator Controller (ACC) 52.1 Description 52.2 Embedded Characteristics 52.3 Block Diagram 52.4 Signal Description 52.5 Product Dependencies 52.5.1 I/O Lines 52.5.2 Power Management 52.5.3 Interrupt 52.5.4 Fault Output 52.6 Functional Description 52.6.1 Description 52.6.2 Analog Settings 52.6.3 Output Masking Period 52.6.4 Fault Mode 52.6.5 Register Write Protection 52.7 Analog Comparator Controller (ACC) User Interface 52.7.1 ACC Control Register 52.7.2 ACC Mode Register 52.7.3 ACC Interrupt Enable Register 52.7.4 ACC Interrupt Disable Register 52.7.5 ACC Interrupt Mask Register 52.7.6 ACC Interrupt Status Register 52.7.7 ACC Analog Control Register 52.7.8 ACC Write Protection Mode Register 52.7.9 ACC Write Protection Status Register 53. Integrity Check Monitor (ICM) 53.1 Description 53.2 Embedded Characteristics 53.3 Block Diagram 53.4 Product Dependencies 53.4.1 Power Management 53.4.2 Interrupt Sources 53.5 Functional Description 53.5.1 Overview 53.5.2 ICM Region Descriptor Structure 53.5.2.1 ICM Region Start Address Structure Member 53.5.2.2 ICM Region Configuration Structure Member 53.5.2.3 ICM Region Control Structure Member 53.5.2.4 ICM Region Next Address Structure Member 53.5.3 ICM Hash Area 53.5.3.1 Message Digest Example 53.5.4 Using ICM as SHA Engine 53.5.4.1 Settings for Simple SHA Calculation 53.5.4.2 Processing Period 53.5.5 ICM Automatic Monitoring Mode 53.5.6 Programming the ICM for Multiple Regions 53.5.7 Security Features 53.6 Integrity Check Monitor (ICM) User Interface 53.6.1 ICM Configuration Register 53.6.2 ICM Control Register 53.6.3 ICM Status Register 53.6.4 ICM Interrupt Enable Register 53.6.5 ICM Interrupt Disable Register 53.6.6 ICM Interrupt Mask Register 53.6.7 ICM Interrupt Status Register 53.6.8 ICM Undefined Access Status Register 53.6.9 ICM Descriptor Area Start Address Register 53.6.10 ICM Hash Area Start Address Register 53.6.11 ICM User Initial Hash Value Register 54. True Random Number Generator (TRNG) 54.1 Description 54.2 Embedded Characteristics 54.3 Block Diagram 54.4 Product Dependencies 54.4.1 Power Management 54.4.2 Interrupt Sources 54.5 Functional Description 54.6 True Random Number Generator (TRNG) User Interface 54.6.1 TRNG Control Register 54.6.2 TRNG Interrupt Enable Register 54.6.3 TRNG Interrupt Disable Register 54.6.4 TRNG Interrupt Mask Register 54.6.5 TRNG Interrupt Status Register 54.6.6 TRNG Output Data Register 55. Advanced Encryption Standard (AES) 55.1 Description 55.2 Embedded Characteristics 55.3 Product Dependencies 55.3.1 Power Management 55.3.2 Interrupt Sources 55.4 Functional Description 55.4.1 AES Register Endianness 55.4.2 Operation Modes 55.4.3 Double Input Buffer 55.4.4 Start Modes 55.4.4.1 Manual Mode 55.4.4.2 Auto Mode 55.4.4.3 DMA Mode 55.4.5 Last Output Data Mode 55.4.5.1 Manual and Auto Modes 55.4.5.2 DMA Mode 55.4.6 Galois/Counter Mode (GCM) 55.4.6.1 Description 55.4.6.2 Key Writing and Automatic Hash Subkey Calculation 55.4.6.3 GCM Processing 55.4.7 Security Features 55.4.7.1 Unspecified Register Access Detection 55.5 Advanced Encryption Standard (AES) User Interface 55.5.1 AES Control Register 55.5.2 AES Mode Register 55.5.3 AES Interrupt Enable Register 55.5.4 AES Interrupt Disable Register 55.5.5 AES Interrupt Mask Register 55.5.6 AES Interrupt Status Register 55.5.7 AES Key Word Register x 55.5.8 AES Input Data Register x 55.5.9 AES Output Data Register x 55.5.10 AES Initialization Vector Register x 55.5.11 AES Additional Authenticated Data Length Register 55.5.12 AES Plaintext/Ciphertext Length Register 55.5.13 AES GCM Intermediate Hash Word Register x 55.5.14 AES GCM Authentication Tag Word Register x 55.5.15 AES GCM Encryption Counter Value Register 55.5.16 AES GCM H Word Register x 56. Electrical Characteristics 56.1 Absolute Maximum Ratings 56.2 DC Characteristics 56.3 Power Consumption 56.3.1 Backup Mode Current Consumption and Wake-Up Time 56.3.2 Sleep Mode Current Consumption and Wake-up Time 56.3.3 Wait Mode Current Consumption and Wake-up Time 56.3.4 Active Mode Power Consumption 56.3.5 Peripheral Power Consumption in Active Mode 56.3.6 I/O Switching Power Consumption 56.4 Oscillator Characteristics 56.4.1 32 kHz RC Oscillator Characteristics 56.4.2 4/8/12 MHz RC Oscillator 56.4.3 32.768 kHz Crystal Oscillator Characteristics 56.4.4 32.768 kHz Crystal Characteristics 56.4.5 XIN32 Clock Characteristics in Bypass Mode 56.4.6 3 to 20 MHz Crystal Oscillator Characteristics 56.4.7 3 to 20 MHz Crystal Characteristics 56.4.8 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode 56.4.9 Crystal Oscillator Design Considerations 56.4.9.1 Choosing a Crystal 56.4.9.2 Printed Circuit Board (PCB) 56.5 PLLA Characteristics 56.6 PLLUSB Characteristics 56.7 USB Transceiver Characteristics 56.8 AFE Characteristics 56.8.1 AFE Power Supply 56.8.1.1 Power Supply Characteristics 56.8.1.2 ADC Bias Current 56.8.2 External Reference Voltage 56.8.3 AFE Timings 56.8.4 AFE Transfer Function 56.8.4.1 Differential Mode (12-bit mode) 56.8.4.2 Single-ended Mode (12-bit mode) 56.8.4.3 Example of LSB Computation 56.8.4.4 Gain and Offset Errors Differential Mode Single-ended Mode 56.8.5 AFE Electrical Characteristics 56.8.6 AFE Channel Input Impedance Track and Hold Time versus Source Output Impedance 56.8.6.1 AFE DAC Offset Compensation 56.8.7 AFE Resolution with Averaging 56.9 Analog Comparator Characteristics 56.10 Temperature Sensor 56.11 12-bit DAC Characteristics 56.12 Embedded Flash Characteristics 56.13 Timings for Worst-Case Conditions 56.13.1 AC Characteristics 56.13.1.1 Processor Clock Characteristics 56.13.1.2 Master Clock Characteristics 56.13.1.3 I/O Characteristics 56.13.1.4 QSPI Characteristics Maximum QSPI Frequency Master Write Mode Master Read Mode QSPI Timings 56.13.1.5 SPI Characteristics Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode SPI Timings 56.13.1.6 HSMCI Timings 56.13.1.7 SDRAM Timings 56.13.1.8 SMC Timings Read Timings Write Timings 56.13.1.9 USART in SPI Mode Timings USART SPI TImings 56.13.1.10 Two-wire Serial Interface Characteristics 56.13.1.11 GMAC Characteristics Timing Conditions Timing Constraints MII Mode RMII Mode 56.13.1.12 SSC Timings Timing Conditions Timing Extraction 56.13.1.13 ISI Timings Timing Conditions Timing Extraction 56.14 Timings for STH Conditions 56.14.1 AC Characteristics 56.14.1.1 Processor Clock Characteristics 56.14.1.2 Master Clock Characteristics 56.14.1.3 I/O Characteristics 56.14.1.4 QSPI Characteristics Maximum QSPI Frequency Master Write Mode Master Read Mode QSPI Timings 56.14.1.5 SPI Characteristics Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode SPI Timings 56.14.1.6 HSMCI Timings 56.14.1.7 SDRAM Timings 56.14.1.8 SMC Timings Read Timings Write Timings 56.14.1.9 USART in SPI Mode Timings USART SPI TImings 56.14.1.10 Two-wire Serial Interface Characteristics 56.14.1.11 GMAC Characteristics Timing Conditions Timing Constraints MII Mode RMII Mode 56.14.1.12 SSC Timings Timing Conditions Timing Extraction 56.14.1.13 ISI Timings Timing Conditions Timing Extraction 57. Mechanical Characteristics 57.1 144-pin LQFP Package 57.2 144-ball LFBGA Package 57.3 144-ball UFBGA Package 57.4 100-pin LQFP Package 57.5 100-ball TFBGA Package 57.6 64-pin LQFP Package 57.7 Soldering Profile 57.8 Packaging Resources 58. Schematic Checklist 58.1 Power Supplies 58.1.1 Supplying the device with only one supply 58.1.2 Supplying the device with two separate supplies 58.2 General Hardware Recommendations 58.2.1 Crystal Oscillators 58.2.2 Serial Wire Debug Interface 58.2.3 Flash Memory 58.2.4 Reset and Test Pins 58.2.5 PIOs 58.2.6 Parallel Capture Mode 58.2.7 Analog Reference, Analog Front-End and DAC 58.2.8 USB Host/Device 58.2.9 Memory Controllers 58.2.10 High Speed Multimedia Card Interface - HSMCI 58.2.11 QSPI Interface 58.2.12 Other Interfaces 58.3 Boot Program Hardware Constraints 58.3.1 Boot Program Supported Crystals (MHz) 58.3.2 SAM-BA Boot 59. Marking 60. Ordering Information 61. Errata 61.1 AFE Controller (AFEC) Issue: AFEC_CSELR write protection Issue: Noise reduces AFEC performance 61.2 AHB Peripheral Port (AHBP) Issue: Access with frequency ratio different from 1 and 1/2 may fail 61.3 AHB Slave Port (AHBS) Issue: Latency on accesses with frequency ratio different from 1 61.4 ARM Cortex-M7 Issue: All issues related to the ARM r0p1 core are described on the ARM site 61.5 Extended DMA Controller (XDMAC) Issue: Issue with byte and half-word accesses to TCM Issue: Issue with byte and half-word accesses with fixed source and fixed destination Issue: DMA request overflow error 61.6 Fast Flash Programming Interface (FFPI) Issue: FFPI programs only 1 MB of Flash 61.7 Inter-IC Sound Controller (I2SC) Issue: I2SC not available 61.8 Master CAN-FD Controller (MCAN) Issue: Flexible data rate feature does not support CRC 61.9 Power Management Controller (PMC) Issue: Wait mode exit from Flash in Standby and Deep-power-down modes may fail 61.10 Quad SPI Interface (QSPI) Issue: QSPI hangs with long DLYCS 61.11 Serial Synchronous Controller (SSC) Issue: Inverted left/right channels Issue: Unexpected delay on TD output 61.12 Supply Controller (SUPC) Issue: SUPC_WUIR write protection 61.13 TWI High Speed (TWIHS) Issue: TWIHS is not compatible with I2C Hold timing Issue: Clear Command does not work 61.14 Universal Synchronous Asynchronous Receiver Transmitter (USART) Issue: Flow Control is not working with DMA 61.15 USB High Speed (USBHS) Issue: USB Host not working in Low-speed mode Issue: USB is not working in 64-pin LQFP package Issue: No DMA for Endpoint 7 62. Revision History Table of Contents
0$ for 10pcs PCB. Register to get $100 free coupons