Datasheet LTC4301 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Supply Independent Hot Swappable 2-Wire Bus Buffer |
| Pages / Page | 12 / 5 — OPERATIO. Start-Up. Input-to-Output Offset Voltage. Propagation Delays. … |
| File Format / Size | PDF / 229 Kb |
| Document Language | English |
OPERATIO. Start-Up. Input-to-Output Offset Voltage. Propagation Delays. Connection Circuitry. Figure 1. Input-Output Connection
Model Line for this Datasheet
Text Version of Document
LTC4301
U OPERATIO Start-Up
and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly When the LTC4301 first receives power on its VCC pin, different than the corresponding card bus waveforms as either during power-up or live insertion, it starts in an described here. undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2.5V (typical).
Input-to-Output Offset Voltage
This is to ensure that the part does not try to function until it has enough voltage to do so. When a logic low voltage, VLOW1, is driven on any of the LTC4301’s data or clock pins, the LTC4301 regulates the During this time, the 1V precharge circuitry is active and voltage on the other side of the device (call it VLOW2) at a forces 1V through 200k nominal resistors to the SDA and slightly higher voltage, as directed by the following SCL pins. Because the I/O card is being plugged into a live equation: backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and V V CC. Precharging LOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical) the SCL and SDA pins to 1V minimizes the worst-case where R is the bus pull-up resistance in ohms. For ex- voltage differential these pins will see at the moment of ample, if a device is forcing SDAOUT to 10mV where VCC connection, therefore minimizing the amount of distur- = 3.3V and the pull-up resistor R on SDAIN is 10k, then the bance caused by the I/O card. voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 = Once the LTC4301 comes out of UVLO, it assumes that 108mV (typical). See the Typical Performance Character- SDAIN and SCLIN have been inserted into a live system istics section for curves showing the offset voltage as a and that SDAOUT and SCLOUT are being powered up at function of VCC and R. the same time as itself. Therefore, it looks for either a stop
Propagation Delays
bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one During a rising edge, the rise time on each side is deter- occurs, the part also verifies that both the SDAOUT and mined by the bus pull-up resistor and the equivalent SCLOUT voltages are high. When all of these conditions capacitance on the line. If the pull-up resistors are the are met, the input-to-output connection circuitry is acti- same, a difference in rise time occurs which is directly vated, joining the SDA and SCL busses on the I/O card with proportional to the difference in capacitance between those on the backplane. the two sides. This effect is displayed in Figure 1 for VCC = 5V and a 10k pull-up resistor on each side (55pF on
Connection Circuitry
one side and 20pF on the other). SDAIN and SCLIN are Once the connection circuitry is activated, the functional- pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled- ity of the SDAIN and SDAOUT pins is identical. A low up to 5V. Since the output side has less capacitance than forced on either pin at any time results in both pin voltages the input, it rises faster and the effective low to high being low. For proper operation, logic low input voltages propagation delay is negative. should be no higher than 0.4V with respect to the ground pin voltage of the LTC4301. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and OUTPUT INPUT SCLOUT. This important feature ensures that clock stretch- SIDE SIDE 20pF 55pF ing, clock synchronization, arbitration and the acknowl- edge protocol always work, regardless of how the devices 1V/DIV in the system are tied to the LTC4301. 4301 F01 Another key feature of the connection circuitry is that it 1µs/DIV provides bidirectional buffering, keeping the backplane
Figure 1. Input-Output Connection
4301fb 5
U OPERATIO Start-Up
and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly When the LTC4301 first receives power on its VCC pin, different than the corresponding card bus waveforms as either during power-up or live insertion, it starts in an described here. undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2.5V (typical).
Input-to-Output Offset Voltage
This is to ensure that the part does not try to function until it has enough voltage to do so. When a logic low voltage, VLOW1, is driven on any of the LTC4301’s data or clock pins, the LTC4301 regulates the During this time, the 1V precharge circuitry is active and voltage on the other side of the device (call it VLOW2) at a forces 1V through 200k nominal resistors to the SDA and slightly higher voltage, as directed by the following SCL pins. Because the I/O card is being plugged into a live equation: backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and V V CC. Precharging LOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical) the SCL and SDA pins to 1V minimizes the worst-case where R is the bus pull-up resistance in ohms. For ex- voltage differential these pins will see at the moment of ample, if a device is forcing SDAOUT to 10mV where VCC connection, therefore minimizing the amount of distur- = 3.3V and the pull-up resistor R on SDAIN is 10k, then the bance caused by the I/O card. voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 = Once the LTC4301 comes out of UVLO, it assumes that 108mV (typical). See the Typical Performance Character- SDAIN and SCLIN have been inserted into a live system istics section for curves showing the offset voltage as a and that SDAOUT and SCLOUT are being powered up at function of VCC and R. the same time as itself. Therefore, it looks for either a stop
Propagation Delays
bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one During a rising edge, the rise time on each side is deter- occurs, the part also verifies that both the SDAOUT and mined by the bus pull-up resistor and the equivalent SCLOUT voltages are high. When all of these conditions capacitance on the line. If the pull-up resistors are the are met, the input-to-output connection circuitry is acti- same, a difference in rise time occurs which is directly vated, joining the SDA and SCL busses on the I/O card with proportional to the difference in capacitance between those on the backplane. the two sides. This effect is displayed in Figure 1 for VCC = 5V and a 10k pull-up resistor on each side (55pF on
Connection Circuitry
one side and 20pF on the other). SDAIN and SCLIN are Once the connection circuitry is activated, the functional- pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled- ity of the SDAIN and SDAOUT pins is identical. A low up to 5V. Since the output side has less capacitance than forced on either pin at any time results in both pin voltages the input, it rises faster and the effective low to high being low. For proper operation, logic low input voltages propagation delay is negative. should be no higher than 0.4V with respect to the ground pin voltage of the LTC4301. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and OUTPUT INPUT SCLOUT. This important feature ensures that clock stretch- SIDE SIDE 20pF 55pF ing, clock synchronization, arbitration and the acknowl- edge protocol always work, regardless of how the devices 1V/DIV in the system are tied to the LTC4301. 4301 F01 Another key feature of the connection circuitry is that it 1µs/DIV provides bidirectional buffering, keeping the backplane
Figure 1. Input-Output Connection
4301fb 5
