Datasheet LTC4303 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Pages / Page | 12 / 5 — PI FU CTIO S. ENABLE (Pin 1):. READY (Pin 5):. SDAIN (Pin 6):. SDAOUT … |
| File Format / Size | PDF / 563 Kb |
| Document Language | English |
PI FU CTIO S. ENABLE (Pin 1):. READY (Pin 5):. SDAIN (Pin 6):. SDAOUT (Pin 7):. SCLOUT (Pin 2):. SCLIN (Pin 3):. CC (Pin 8):
Model Line for this Datasheet
Text Version of Document
LTC4303
U U U PI FU CTIO S ENABLE (Pin 1):
Connection Enable. This is a digital
READY (Pin 5):
Connection Status Flag. READY provides threshold input pin. For normal operation ENABLE is high. a digital fl ag which indicates the status of the connection Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, circuitry described in the “Connection Circuitry” section. SCLIN from SCLOUT, asserts READY low and disables Connect a resistor of 10k to VCC to provide the pull-up. automatic clocking. A rising edge on ENABLE after a fault
SDAIN (Pin 6):
Serial Data Input. Connect this pin to the has occurred unconditionally forces a connection between SDA bus on the backplane. SDAIN, SDAOUT and SCLIN, SCLOUT.
SDAOUT (Pin 7):
Serial Data Output. Connect this pin to
SCLOUT (Pin 2):
Serial Clock Output. Connect this pin to the SDA bus on the card. the SCL bus on the card.
V SCLIN (Pin 3):
Serial Clock Input. Connect this pin to SCL
CC (Pin 8):
Supply Voltage Input. Place a bypass capacitor of at least 0.01µF close to V on the bus backplane. CC for best results.
Exposed Pad (Pin 9, DFN Only):
Exposed pad may be left
GND (Pin 4):
Device Ground. Connect this pin to a ground open or connected to the ground plane. plane for best results.
W BLOCK DIAGRA LTC4303 2-Wire Bus Buffer with Stuck Bus Protection
3.5mA 3.5mA SLEW RATE SLEW RATE CONNECT 8 VCC DETECTOR DETECTOR SDAIN SDAOUT 6 7 200k PC_CONNECT PC_CONNECT 200k PRECHARGE 3.5mA 3.5mA SLEW RATE SLEW RATE 200k DETECTOR CONNECT 200k DETECTOR SCLIN SCLOUT 3 2 + + – – 30ms AUTOMATIC UVLO TIMER CLOCKING + 1.8V – LOGIC PC_CONNECT – 1.8V + READY CONNECT 5 ENABLE 1 + 95ms UVLO DELAY CONNECT GND 1.4V – 4 4301 BD 4303fb 5
U U U PI FU CTIO S ENABLE (Pin 1):
Connection Enable. This is a digital
READY (Pin 5):
Connection Status Flag. READY provides threshold input pin. For normal operation ENABLE is high. a digital fl ag which indicates the status of the connection Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, circuitry described in the “Connection Circuitry” section. SCLIN from SCLOUT, asserts READY low and disables Connect a resistor of 10k to VCC to provide the pull-up. automatic clocking. A rising edge on ENABLE after a fault
SDAIN (Pin 6):
Serial Data Input. Connect this pin to the has occurred unconditionally forces a connection between SDA bus on the backplane. SDAIN, SDAOUT and SCLIN, SCLOUT.
SDAOUT (Pin 7):
Serial Data Output. Connect this pin to
SCLOUT (Pin 2):
Serial Clock Output. Connect this pin to the SDA bus on the card. the SCL bus on the card.
V SCLIN (Pin 3):
Serial Clock Input. Connect this pin to SCL
CC (Pin 8):
Supply Voltage Input. Place a bypass capacitor of at least 0.01µF close to V on the bus backplane. CC for best results.
Exposed Pad (Pin 9, DFN Only):
Exposed pad may be left
GND (Pin 4):
Device Ground. Connect this pin to a ground open or connected to the ground plane. plane for best results.
W BLOCK DIAGRA LTC4303 2-Wire Bus Buffer with Stuck Bus Protection
3.5mA 3.5mA SLEW RATE SLEW RATE CONNECT 8 VCC DETECTOR DETECTOR SDAIN SDAOUT 6 7 200k PC_CONNECT PC_CONNECT 200k PRECHARGE 3.5mA 3.5mA SLEW RATE SLEW RATE 200k DETECTOR CONNECT 200k DETECTOR SCLIN SCLOUT 3 2 + + – – 30ms AUTOMATIC UVLO TIMER CLOCKING + 1.8V – LOGIC PC_CONNECT – 1.8V + READY CONNECT 5 ENABLE 1 + 95ms UVLO DELAY CONNECT GND 1.4V – 4 4301 BD 4303fb 5
