Datasheet ADXL356, ADXL357 (Analog Devices) - 22

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ADXL356/ADXL357 Data Sheet AXES OF ACCELERATION SENSITIVITY
external ADCs, use V1P8ANA as the reference voltage. The digital Figure 60 shows the axes of acceleration sensitivity. Note that output ADXL357 includes ADCs that are ratiometric to V1P8ANA, the output voltage increases when accelerated along the thereby rendering offset and sensitivity insensitive to the value sensitive axis. of V1P8ANA. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage.
Z V1P8DIG Y
V1P8DIG is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. If driven externally, V1P8DIG must be the same voltage as the V1P8ANA voltage.
VDDIO
059 The VDDIO value determines the logic high levels. On the analog
X
15429- output ADXL356, VDDIO sets the logic high level for the self test Figure 60. Axes of Acceleration Sensitivity pins, ST1 and ST2, as well as the STBY pin. On the digital output
POWER SEQUENCING
ADXL357, VDDIO sets the logic high level for communications There are two methods for applying power to the device. interface ports, as wel as the interrupt and DRDY outputs. Typically, internal LDO regulators generate the 1.8 V power for The LDO regulators are operational when VSUPPLY is between the analog and digital supplies, V 2.25 V and 3.6 V. V 1P8ANA and V1P8DIG, respectively. 1P8ANA and V1P8DIG are the regulator outputs in Optionally, connecting V this mode. Alternatively, when tying V SUPPLY to VSS and driving V1P8ANA and SUPPLY to VSS, V1P8ANA and V V 1P8DIG with an external supply can supply V1P8ANA and V1P8DIG. 1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range. When using the internal LDO regulators, connect V
OVERRANGE PROTECTION
SUPPLY to a voltage source between 2.25 V to 3.6 V. In this case, VDDIO and To avoid electrostatic capture of the proof mass when the VSUPPLY can be powered in paral el. VSUPPLY must not exceed the accelerometer is subject to input acceleration beyond its ful - VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be scale range, all sensor drive clocks turn off for 0.5 ms. In the powered before VSUPPLY. ±10 g/±10.24 g range setting, the overrange protection activates When disabling the internal LDO regulators and using an external for input signals beyond approximately ±40 g (±25%), and for 1.8 V supply to power V the ±20 g/±20.48 g and ±40 g/±40.95 g range settings, the 1P8ANA and V1P8DIG, tie VSUPPLY to ground, and set V threshold corresponds to about ±80 g (±25%). 1P8ANA and V1P8DIG to the same final voltage level. In the case of bypassing the LDOs, the recommended power sequence is When overrange protection occurs, the X to apply power to V OUT, YOUT, and ZOUT pins DDIO, followed by V1P8DIG approximately 10 µs on the ADXL356 begin to drive to midscale. The ADXL357 later, and then V1P8ANA approximately 10 µs later. If necessary, floats toward zero, and first in, first out (FIFO) buffer begins V1P8DIG and VDDIO can be powered from the same 1.8 V supply, filling with this data. which can also be tied to V1P8ANA with proper isolation. In this case, proper decoupling and low frequency isolation is important
SELF TEST
to maintain the noise performance of the sensor. The ADXL356 and ADXL357 incorporate a self test feature
POWER SUPPLY DESCRIPTION
that effectively tests the mechanical and electronic system. Enabling self test stimulates the sensor electrostatically to The ADXL356/ADXL357 have four different power supply produce an output corresponding to the test signal applied as domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal well as the mechanical force exerted. Only the z-axis response is analog and digital circuitry operates at 1.8 V nominal. specified to validate device functionality.
VSUPPLY
In the ADXL356, drive the ST1 pin to VDDIO to invoke self test VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two mode. Then, by driving the ST2 pin to VDDIO, the ADXL356 LDO regulators that generate the nominal 1.8 V outputs for applies an electrostatic force to the mechanical sensor and V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO induces a change in output in response to the force. The self test regulators, which al ows driving V1P8ANA and V1P8DIG from an delta (or response) is the difference in output voltage in the external source. z-axis when ST2 is high vs. ST2 is low, while ST1 is asserted.
V
After the self test measurement is complete, bring both pins low
1P8ANA
to resume normal operation. All sensor and analog signal processing circuitry operates in this domain. Offset and sensitivity of the analog output The self test operation is similar in the ADXL357, except ST1 ADXL356 are ratiometric to this supply voltage. When using and ST2 can be accessed through the SELF_TEST register (Register 0x2E). Rev. 0 | Page 22 of 42 Document Outline Features Applications Functional Block Diagrams General Description Revision History Specifications Analog Output for the ADXL356 Digital Output for the ADXL357 SPI Digital Interface Characteristics for the ADXL357 I2C Digital Interface Characteristics for the ADXL357 Absolute Maximum Ratings Thermal Resistance Recommended Soldering Profile ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Root Allan Variance (RAV) ADXL357 Characteristics Theory of Operation Applications Information Analog Output Digital Output Axes of Acceleration Sensitivity Power Sequencing Power Supply Description VSUPPLY V1P8ANA V1P8DIG VDDIO Overrange Protection Self Test Filter Serial Communications SPI Protocol I2C Protocol Reading Acceleration or Temperature Data from the Interface FIFO Interrupts DATA_RDY DRDY Pin FIFO_FULL FIFO_OVR Activity NVM_BUSY External Synchronization and Interpolation EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock, No Interpolation Filter ADXL357 Register Map Register Definitions Analog Devices ID Register Address: 0x00, Reset: 0xAD, Name: DEVID_AD Analog Devices MEMS ID Register Address: 0x01, Reset: 0x1D, Name: DEVID_MST Device ID Register Address: 0x02, Reset: 0xED, Name: PARTID Product Revision ID Register Address: 0x03, Reset: 0x01, Name: REVID Status Register Address: 0x04, Reset: 0x00, Name: Status FIFO Entries Register Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES Temperature Data Registers Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-Axis Data Registers Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-Axis Data Registers Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-Axis Data Registers Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO Access Register Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-Axis Offset Trim Registers Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-Axis Offset Trim Registers Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-Axis Offset Trim Registers Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Activity Enable Register Address: 0x24, Reset: 0x00, Name: ACT_EN Activity Threshold Registers Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Activity Count Register Address: 0x27, Reset: 0x01, Name: ACT_COUNT Filter Settings Register Address: 0x28, Reset: 0x00, Name: Filter FIFO Samples Register Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES Interrupt Pin (INTx) Function Map Register Address: 0x2A, Reset: 0x00, Name: INT_MAP Data Synchronization Address: 0x2B, Reset: 0x00, Name: Sync I2C Speed, Interrupt Polarity, and Range Register Address: 0x2C, Reset: 0x81, Name: Range Power Control Register Address: 0x2D, Reset: 0x01, Name: POWER_CTL Self Test Register Address: 0x2E, Reset: 0x00, Name: SELF_TEST Reset Register Address: 0x2F, Reset: 0x00, Name: Reset PCB Footprint Pattern Outline Dimensions Ordering Guide