Datasheet ADXL372 (Analog Devices) - 51

ADXL372 Data Sheet INT2 FUNCTION MAP REGISTER Address: 0x3C, Reset: 0x00, Name: INT2_MAP
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 ] IN T 2 _LO W ( R/W ) [ 0 ] D AT A_RD Y_IN T 2 ( R/W )
Co nfig ure s INT2 fo r ac tiv e lo w o p e ratio n. Map d ata re ad y inte rrup t o nto INT2 .
[ 6 ] AW AKE_IN T 2 ( R/W ) [ 1 ] FIFO _RD Y_IN T 2 ( R/W )
Map aw ak e inte rrup t o nto INT2 . Map FIFO_READY inte rrup t o nto INT2 .
[ 5 ] ACT 2 _IN T 2 ( R/W ) [ 2 ] FIFO _FULL_IN T 2 ( R/W )
Map ac tiv ity 2 inte rrup t o nto INT2 . Map FIFO_FULL inte rrup t o nto INT2 .
[ 4 ] IN ACT _IN T 2 ( R/W ) [ 3 ] FIFO _O V R_IN T 2 ( R/W )
Map inac tiv ity inte rrup t o nto INT2 . Map FIFO_OVERRUN inte rrup t o nto INT2 .
Table 63. Bit Descriptions for INT2_MAP Bits Bit Name Settings Description Reset Access
7 INT2_LOW Configures INT2 for active low operation. 0x0 R/W 6 AWAKE_INT2 Map awake interrupt onto INT2. 0x0 R/W 5 ACT2_INT2 Map Activity 2 (motion warning) interrupt onto INT2. 0x0 R/W 4 INACT_INT2 Map inactivity interrupt onto INT2. 0x0 R/W 3 FIFO_OVR_INT2 Map FIFO_OVERRUN interrupt onto INT2. 0x0 R/W 2 FIFO_FULL_INT2 Map FIFO_FULL interrupt onto INT2. 0x0 R/W 1 FIFO_RDY_INT2 Map FIFO_READY interrupt onto INT2. 0x0 R/W 0 DATA_RDY_INT2 Map data ready interrupt onto INT2. 0x0 R/W
EXTERNAL TIMING CONTROL REGISTER Address: 0x3D, Reset: 0x00, Name: TIMING
Use this register to control the ADXL372 timing parameters: ODR and external timing triggers. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :5 ] O D R ( R/W ) [ 0 ] EX T _S YN C ( R/W )
Outp ut d ata rate . Enab le e x te rnal trig g e r. 0 0 0 : 4 0 0 Hz ODR. 0 0 1: 8 0 0 Hz ODR.
[ 1 ] EX T _CLK ( R/W )
0 10 : 16 0 0 Hz ODR. Enab le e x te rnal c lo c k . 0 11: 3 2 0 0 Hz ODR. 10 0 : 6 4 0 0 Hz ODR.
[ 4 :2 ] W AKEUP _RAT E ( R/W )
Tim e r Rate fo r Wak e -Up Mo d e . 0 : 5 2 m s . 1: 10 4 m s . 10 : 2 0 8 m s . 11: 5 12 m s . 10 0 : 2 0 4 8 m s . 10 1: 4 0 9 6 m s . 110 : 8 19 2 m s . 111: 2 4 5 7 6 m s .
Table 64. Bit Descriptions for TIMING Bits Bit Name Settings Description Reset Access
[7:5] ODR Output data rate. 0x0 R/W 000 400 Hz ODR. 001 800 Hz ODR. 010 1600 Hz ODR. 011 3200 Hz ODR. 100 6400 Hz ODR. Rev. 0 | Page 50 of 56 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE RECOMMENDED SOLDERING PROFILE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION MECHANICAL DEVICE OPERATION OPERATING MODES Measurement Mode Instant On Mode Wake-Up Mode Standby BANDWIDTH Low-Pass Antialiasing Filter High-Pass Filter Filter Settling Time Selectable ODR POWER/NOISE TRADE-OFF POWER SAVINGS AUTONOMOUS EVENT DETECTION ACTIVITY AND INACTIVITY Low-Pass Activity Detect Filter Activity Detection Referenced and Absolute Configurations Activity Timer Activity Detection in Wake-Up Mode Inactivity Detection Referenced and Absolute Configurations Inactivity Timer Linking Activity and Inactivity Detection Default Mode Linked Mode Loop Mode Autosleep Using the AWAKE Bit MOTION WARNING IMPACT DETECTION FEATURES WIDE BANDWIDTH INSTANT ON IMPACT DETECTION CAPTURING IMPACT EVENTS FIFO BENEFITS OF THE FIFO System Level Power Savings Data Recording/Event Context USING THE FIFO FIFO Disabled Oldest Saved Mode (First N) Stream Mode (Last N) Triggered Mode RETRIEVING DATA FROM FIFO INTERRUPTS INTERRUPT PINS Alternate Functions TYPES OF INTERRUPTS Activity and Inactivity Interrupts Data Ready Interrupt FIFO Interrupts FIFO Watermark FIFO Ready Overrun ADDITIONAL FEATURES USING AN EXTERNAL CLOCK SYNCHRONIZED DATA SAMPLING SELF TEST Self Test Procedure USER REGISTER PROTECTION USER OFFSET TRIMS SERIAL COMMUNICATIONS SERIAL INTERFACE SPI Protocol I2C Protocol MULTIBYTE TRANSFERS INVALID ADDRESSES AND ADDRESS FOLDING SPI Timing Diagrams I2C Timing Diagrams REGISTER MAP REGISTER DETAILS ANALOG DEVICES ID REGISTER ANALOG DEVICES MEMS ID REGISTER DEVICE ID REGISTER PRODUCT REVISION ID REGISTER STATUS REGISTER ACTIVITY STATUS REGISTER FIFO ENTRIES REGISTER, MSB FIFO ENTRIES REGISTER, LSB X-AXIS DATA REGISTER, MSB X-AXIS DATA REGISTER, LSB Y-AXIS DATA REGISTER, MSB Y-AXIS DATA REGISTER, LSB Z-AXIS DATA REGISTER, MSB Z-AXIS DATA REGISTER, LSB HIGHEST PEAK DATA REGISTERS X-AXIS HIGHEST PEAK DATA REGISTER, MSB X-AXIS HIGHEST PEAK DATA REGISTER, LSB Y-AXIS HIGHEST PEAK DATA REGISTER, MSB Y-AXIS HIGHEST PEAK DATA REGISTER, LSB Z-AXIS HIGHEST PEAK DATA REGISTER, MSB Z-AXIS HIGHEST PEAK DATA REGISTER, LSB OFFSET TRIM REGISTERS X-AXIS OFFSET TRIM REGISTER, LSB Y-AXIS OFFSET TRIM REGISTER, LSB Z-AXIS OFFSET TRIM REGISTER, LSB X-AXIS ACTIVITY THRESHOLD REGISTER, MSB X-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Y-AXIS ACTIVITY THRESHOLD REGISTER, MSB Y-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Z-AXIS ACTIVITY THRESHOLD REGISTER, MSB Z-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB ACTIVITY TIME REGISTER X-AXIS INACTIVITY THRESHOLD REGISTER, MSB X-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Y-AXIS INACTIVITY THRESHOLD REGISTER, MSB Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Z-AXIS INACTIVITY THRESHOLD REGISTER, MSB Z-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB INACTIVITY TIME REGISTERS INACTIVITY TIMER REGISTER, MSB INACTIVITY TIMER REGISTER, LSB X-AXIS MOTION WARNING THRESHOLD REGISTER, MSB X-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Y-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Y-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Z-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB HIGH-PASS FILTER SETTINGS REGISTER FIFO SAMPLES REGISTER FIFO CONTROL REGISTER INTERRUPT PIN FUNCTION MAP REGISTERS INT2 FUNCTION MAP REGISTER EXTERNAL TIMING CONTROL REGISTER MEASUREMENT CONTROL REGISTER POWER CONTROL REGISTER SELF TEST REGISTER RESET (CLEARS) REGISTER, PART IN STANDBY MODE FIFO ACCESS REGISTER APPLICATIONS INFORMATION APPLICATION EXAMPLES Power Supply Decoupling Using External Timing Triggers OPERATION AT VOLTAGES OTHER THAN 2.5 V OPERATION AT TEMPERATURES OTHER THAN AMBIENT MECHANICAL CONSIDERATIONS FOR MOUNTING AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE