Datasheet ADIS16201 (Analog Devices) - 28

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Data Sheet ADIS16201 PERIPHERALS AUXILIARY ADC FUNCTION AUXILIARY DAC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC The auxiliary DAC function integrates a standard 12-bit DAC into the ADIS16201 to digitize other system-level analog signals. into the ADIS16201. The DAC output is buffered and fed off- The output of the ADC can be monitored through the AUX_ADC chip to al ow for the control of miscel aneous system-level control register, as defined in Table 6 and Table 7. The ADC functions. Data is downloaded through the writing of two consists of a 12-bit successive approximation converter. The adjacent data bytes, as defined in its register definition. To output data is presented in straight binary format, with the ful prevent the DAC from transitioning through inadvertent states scale range extending from 0 V to VREF. A high precision, low during data downloads, a single command is used to drift, factory-calibrated 2.5 V reference is also provided. simultaneously latch both data bytes into the DAC after they have been written into the AUX_DAC control register. This Figure 38 shows the equivalent circuit of the analog input command is implemented by writing 1 to Bit 2 of the command structure of the ADC. The input capacitor, C1, is typically 4 pF control register, which, once received, results in the DAC output and can be attributed to parasitic package capacitance. The two transitioning to the desired state. diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed The DAC output provides an output range of 0 V to 2.5 V. The the supply rails by more than 300 mV. This would cause these DAC output buffer features a true rail-to-rail output stage. This diodes to become forward-biased and start conducting. They means that, unloaded, the output is capable of reaching within can handle 10 mA without causing irreversible damage to the 5 mV of ground. Moreover, the DAC’s linearity performance part. The resistor is a lumped component that represents the on (when driving a 5 kΩ resistive load to ground) is good through resistance of the switches. The value of this resistance is typical y the ful transfer function, except for Code 0 to Code 100. 100 Ω. Capacitor C2 represents the ADC sampling capacitor Linearity degradation near ground is caused by saturation of the and is typical y 16 pF. output amplifier. As the output is forced to sink more current, the nonlinear region at the bottom of the transfer function
VDD
becomes larger. Larger current demands can significantly limit
D C2 R1
output voltage swing.
C1 D AUX_DAC Register Definition
038
Address Default1 Format Access
05462- Figure 38. Equivalent Analog Input Circuit 0x31, 0x30 0x0000 Binary R/W Conversion Phase: Switch Open Track Phase: Switch Closed 1 Default is valid only until the first register write cycle. For ac applications, removing high frequency components from The AUX_DAC register controls the ADIS16201’s DAC function. the analog input signal is recommended through the use of an The data bits provide a 12-bit binary format number with 0 RC low-pass filter on the relevant analog input pins. representing 0 V and 0x0FFFh representing 2.5 V. The data within this register is volatile and is set to 0s upon reset. This In applications where harmonic distortion and signal-to-noise register has read/write capability. ratio are critical, the analog input should be driven from a low
Table 30. AUX_DAC Bit Descriptions
impedance source. Large source impedances significantly affect
Bit Description
the ac performance of the ADC. This can necessitate the use of 15:12 Not used an input buffer amplifier. When no input amplifier is used to 11:0 Data bits drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. Rev. C | Page 27 of 32 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Accelerometer Operation Inclinometer Operation Temperature Sensor Basic Operation Data Output Register Access Programming and Control Control Register Overview Control Register Access Control Register Details Calibration Calibration Register Definitions XACCL_OFF Register Definition XACCL_SCALE Register Definition YACCL_OFF Register Definition YACCL_SCALE Register Definition XINCL_OFF Register Definition XINCL_SCALE Register Definition YINCL_OFF Register Definition YINCL_SCALE Register Definition Alarms ALM_MAG1 Register Definition ALM_SMPL1 Register Definition ALM_MAG2 Register Definition ALM_SMPL2 Register Definition ALM_CTRL Register Definition Sample Period Control SMPL_PRD Register Definition Filtering Control AVG_CNT Register Definition Power-Down Control PWR_MDE Register Definition Status Feedback STATUS Register Definition Command Control COMMAND Register Definition Miscellaneous Control Register MSC_CTRL Register Definition Peripherals Auxiliary ADC Function Auxiliary DAC Function AUX_DAC Register Definition General Purpose I/O Control GPIO_CTRL Register Definition Applications Serial Peripheral Interface (SPI) Hardware Considerations Grounding and Board Layout Recomendations Bandgap Reference Power-On Reset Operation Second-Level Assembly Example Pad Layout Outline Dimensions Ordering Guide