Datasheet MCP9902, MCP9903, MCP9904 (Microchip) - 10
| Manufacturer | Microchip |
| Description | Multi-Channel Low-Temperature Remote Diode Sensor |
| Pages / Page | 50 / 10 — MCP9902/3/4. 4.4. THERM Output. 4.6. ALERT/THERM2 Output. 4.5. THERM Pin … |
| File Format / Size | PDF / 510 Kb |
| Document Language | English |
MCP9902/3/4. 4.4. THERM Output. 4.6. ALERT/THERM2 Output. 4.5. THERM Pin Address Decoding. TABLE 4-2:. I2C/SMBUS ADDRESS. DECODE
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MCP9902/3/4 4.4 THERM Output 4.6 ALERT/THERM2 Output
The THERM output is asserted independently of the 4.6.1 ALERT/THERM2 PIN INTERRUPT ALERT output and cannot be masked. Whenever any MODE of the measured temperatures exceed the user programmed Therm Limit values for the programmed When configured to operate in interrupt mode, the ALERT/THERM2 pin asserts low when an out-of-limit number of consecutive measurements, the THERM measurement (> high limit or < low limit) is detected on output is asserted. Once it has been asserted, it wil remain asserted until all measured temperatures drop any diode or when an external diode fault is detected. The ALERT/THERM2 pin will remain asserted as long below the Therm Limit minus the Therm Hysteresis as an out-of-limit condition remains. Once the (also programmable). out-of-limit condition has been removed, the When the THERM output is asserted, the THERM ALERT/THERM2 pin will remain asserted until the status bits wil likewise be set. Reading these bits wil appropriate status bits are cleared. not clear them until the THERM output is deasserted. The ALERT/THERM2 pin can be masked by setting Once the THERM output is deasserted, the THERM status bits will be automatically cleared. the MASK_ALL bit. Once the ALERT/THERM2 pin has been masked, it will be deasserted and remain deas- serted until the MASK_ALL bit is cleared by the user.
4.5 THERM Pin Address Decoding
Any interrupt conditions that occur while the The Address decode is performed by pulling known ALERT/THERM2 pin is masked wil update the Status currents from V Register normally. There are also individual channel DD through the external resistor causing the pin voltage to drop based on the masks (see Register 5-20). respective current/resistor relationship. This pin The ALERT/THERM2 pin is used as an interrupt signal voltage is compared against a threshold that or as an SMBus Alert signal that allows an SMBus determines the value of the pull-up resistor. slave to communicate an error condition to the master. The MCP9902/3/4-A SMBus slave address is deter- One or more ALERT/THERM2 Outputs can be mined by the pull-up resistor on the THERM/ADDR pin hard-wired together. as shown in Table 4-2. 4.6.2 ALERT/THERM2 PIN IN THERM
TABLE 4-2: I2C/SMBUS ADDRESS
MODE
DECODE
When the ALERT/THERM2 pin is configured to oper- ate in THERM mode, it will be asserted if any of the
Pull Up Resistor on SMBus Address
measured temperatures exceeds the respective high
THERM pin (±5%)
limit. The ALERT/THERM2 pin will remain asserted 4.7 kΩ 1111_100 (r/w)b until all temperatures drop below the corresponding 6.8 kΩ 1011_100 (r/w)b high limit minus the Therm Hysteresis value. 10 kΩ 1001_100 (r/w)b When the ALERT/THERM2 pin is asserted in THERM mode, the corresponding high limit status bits wil be 15 kΩ 1101_100 (r/w)b set. Reading these bits will not clear them until the 22 kΩ 0011_100 (r/w)b ALERT/THERM2 pin is deasserted. Once the 33 kΩ 0111_100 (r/w)b ALERT/THERM2 pin is deasserted, the status bits wil The MCP9902-1 I2C/SMBus address is hard coded to be automatically cleared. 1001_100(r/w). The MASK_ALL bit wil not block the ALERT/THERM2 The MCP9902-2 I2C/SMBus address is hard coded to pin in this mode; however, the individual channel 1001_101(r/w). masks (see Register 5-20) will prevent the respective The MCP9903-1 I2C/SMBus address is hard coded to channel from asserting the ALERT/THERM2 pin. 1001_100(r/w). 4.6.3 DEFAULT POWER UP CONDITIONS The MCP9903-2 I2C/SMBus address is hard coded to On power-up, the ALERT/THERM2 is disabled and the 1001_101(r/w). MASK ALL (MSKAL) bit in the CONFIG register (see The MCP9904-1 I2C/SMBus address is hard coded to Register 5-6) is set. Additionally, an artificial fault has 1001_100(r/w). been placed in the device, and is enabled at power up. The MCP9904-2 I2C/SMBus address is hard coded to The FAULT TEST (FT_TST) bit in the Fault Status reg- 1001_101(r/w). ister (see Register 5-20) will allow the assertion of the ALERT/THERM2 pin when this test mode is enabled once MSKAL is cleared. To use the ALERT/THERM2 functions described in this section, the MSKAL bit must be set to ‘0’, and the FT_TST bit to ‘1’ in order for the pin to function properly. DS20005382C-page 10 2015-2016 Microchip Technology Inc. Document Outline Multi-Channel Low-Temperature Remote Diode Sensor Features Typical Applications Description Package Types MCP9902/3/4 Functional Block Diagram 1.0 Electrical Characteristics 1.1 Electrical Specifications Absolute Maximum Ratings 1.2 DC Characteristics 1.3 Thermal Specifications FIGURE 1-1: POR and POR Rearm With Slow Rising VDD. 1.4 SMBUS Module Specifications FIGURE 1-2: SMBus Timing Diagram. 2.0 Typical Operating Curves FIGURE 2-1: Supply Current vs. Conversion Rate (TA = +25°C, VDD = 3.3V). FIGURE 2-2: IDD vs. Temperature. FIGURE 2-3: Temperature Error vs. Filter Capacitor (VDD = 3.3V, TA = TD = +25°C, 2N3904). FIGURE 2-4: Temperature Error vs. Ambient Temperature (VDD = 3.3V, TD = +25°C, 16 Units, 2N3904). FIGURE 2-5: Temperature Error vs. Remote Temperature. (VDD = 3.3V, TD = +25°C, 16 Units, 2N3904). FIGURE 2-6: Temperature Error vs. Series Resistance (TA = +25°C, VDD = 3.3V). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Power Supply (VDD) 3.2 Diode 1 Pair (DN1/DP1) 3.3 Diode 2 Pair (DN2/DP2) 3.4 Anti-Parallel Diode Pair (DN3/DP2 and DN2/DP3) (MCP9904 only) 3.5 THERM LIMIT ALERT (THERM/ADDR) 3.6 Ground (GND) 3.7 Maskable ALERT (ALERT/THERM2) 3.8 SMBus Data (SMDATA) 3.9 SMBus Clock (SMCLK) 3.10 Exposed Thermal Pad (EP) 4.0 Functional Description FIGURE 4-1: MCP9902/3/4 System Diagram. 4.1 Power States 4.2 Conversion Rates TABLE 4-1: Conversion Rate 4.3 Dynamic Averaging 4.4 THERM Output 4.5 THERM Pin Address Decoding TABLE 4-2: I2C/SMBus Address Decode 4.6 ALERT/THERM2 Output 4.7 Temperature Measurement 4.8 Beta Compensation 4.9 Resistance Error Correction (REC) 4.10 Programmable External Diode Ideality Factor TABLE 4-3: Ideality Factor Look-Up Table (Diode Model) TABLE 4-4: Substrate Diode Ideality Factor Look-Up Table (BJT Model) 4.11 Diode Faults 4.12 Consecutive Alerts TABLE 4-5: Consecutive Alert/ THERM Settings 4.13 Limit Register Interaction 4.14 Digital Filter TABLE 4-6: Filter Settings FIGURE 4-2: Temperature Filter Step Response. FIGURE 4-3: Temperature Filter Impulse Response. 4.15 Temperature Measurement Results and Data TABLE 4-7: Temperature Data Format 5.0 Communications Protocol 5.1 SMBus Control Bits 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus Protocols TABLE 5-1: Protocol Format TABLE 5-2: Write Byte Protocol TABLE 5-3: Read Byte Protocol TABLE 5-4: Send Byte Protocol TABLE 5-5: Receive Byte Protocol 5.5 Alert Response Address TABLE 5-6: Alert Response Address Protocol 5.6 Register Description TABLE 5-7: Register Set in Hexadecimal Order (Continued) 5.7 Data Read Interlock Register 5-1: iNT TEMP HI BYTE: Internal Diode High Byte Temperature Data Register (ADDRESS 00h) Register 5-2: INT temp LO byte: Internal Diode LOW Byte Temperature Data Register (ADDRESS 29h) Register 5-3: EXT(n) TEMP hi byte: EXTERNAL Diode High Byte Temperature Data Register (Addresses 01h, 23h, 2Ah) Register 5-4: EXT(n) TEMP Lo Byte: EXTERNAL Diode LOW Byte Temperature Data Register (Addresses 10h, 24h, 2Bh) Register 5-5: Status: status register reporting state of internal and external diodes (ADDRESS 02h) Register 5-6: CONFIG: Configuration Register (Addresses 03h and 09h) Register 5-7: CONVERT: TEMPERATURE CONVERSION RATE REGISTER (ADDRESS 04h, 0AH) Register 5-8: int diode hi limit temp: INTERNAL DIODE HIGH LIMIT TEMPERATURE REGISTER (Addresses 05h and 0Bh) Register 5-9: int diode lo lim TEMP – INTERNAL DIODE LOW LIMIT TEMPERATURE REGISTER (addresses 06H AND 0CH) Register 5-10: EXT(n) hi lim temp HB – EXTERNAL DIODE N HIGH TEMPERATURE LIMIT, high byte REGISTER (addresses 07h and 0dh, 15h, 2Ch) Register 5-11: EXT(n) hi lim LB – EXTERNAL DIODE N HIGH LIMIT TEMPERATURE, low byte REGISTER (Addresses 13H, 17h, 2eh) Register 5-12: EXT(n) lo lim HB – EXTERNAL DIODE N low LIMIT, high byte TEMPERATURE REGISTER (addresses 08h and 0eh, 16h, 2Dh) Register 5-13: EXT(N) LO lim LB – EXTERNAL DIODE N LOW LIMIT, low byte TEMPERATURE REGISTER (Addresses 14H, 18h, 2fh) Register 5-14: scrtchpd(N): sCRATCHPAD REGISTER (addresses 11H AND 12H) Register 5-15: ONE SHOT – ONE-shot temperature conversion initiation REGISTER (address 0fh) Register 5-16: EXT(n) THrm lim – external diode (N) therm limit REGISTER (addresses 19h, 1Ah and 30h) Register 5-17: iNTD THrm lim – internal diode therm limit REGISTER (address 20h) Register 5-18: THRM HYS – therm limit hysteresis REGISTER (address 21h) Register 5-19: EXT FLT STS – external diode fault status REGISTER (address 1Bh) Register 5-20: DIODE FAULT MASK – diode fault mask REGISTER (address 1Fh) Register 5-21: CONSEC ALERT – Consecutive Alert Register (address 22h) Register 5-22: ext(N) beta cfg – beta compensation configuration Register (addresses 25h and 26h) Register 5-23: ext (n) IDEALITY FACTOR – External Diode N Ideality Factor Register (addresses 27h, 28h and 31h) Register 5-24: HI LIM STS – High Limit Status Register (address 35h) Register 5-25: LO LIM STS – Low Limit Status Register (address 36h) Register 5-26: THRM LIM STS – High Limit Status Register (address 37h) Register 5-27: FLTR SEL: Filter Selection Register (address 40h) Register 5-28: PROD_ID – Product ID Register (address FDh) Register 5-29: MCHP_ID – Manufacturer ID Register (address FEh) Register 5-30: REVISION – Revision Register (address FFh) 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Revision C (July 2016) Revision B (March 2016) Revision A (December 2015) Product Identification System Trademarks Worldwide Sales and Service
MCP9902/3/4 4.4 THERM Output 4.6 ALERT/THERM2 Output
The THERM output is asserted independently of the 4.6.1 ALERT/THERM2 PIN INTERRUPT ALERT output and cannot be masked. Whenever any MODE of the measured temperatures exceed the user programmed Therm Limit values for the programmed When configured to operate in interrupt mode, the ALERT/THERM2 pin asserts low when an out-of-limit number of consecutive measurements, the THERM measurement (> high limit or < low limit) is detected on output is asserted. Once it has been asserted, it wil remain asserted until all measured temperatures drop any diode or when an external diode fault is detected. The ALERT/THERM2 pin will remain asserted as long below the Therm Limit minus the Therm Hysteresis as an out-of-limit condition remains. Once the (also programmable). out-of-limit condition has been removed, the When the THERM output is asserted, the THERM ALERT/THERM2 pin will remain asserted until the status bits wil likewise be set. Reading these bits wil appropriate status bits are cleared. not clear them until the THERM output is deasserted. The ALERT/THERM2 pin can be masked by setting Once the THERM output is deasserted, the THERM status bits will be automatically cleared. the MASK_ALL bit. Once the ALERT/THERM2 pin has been masked, it will be deasserted and remain deas- serted until the MASK_ALL bit is cleared by the user.
4.5 THERM Pin Address Decoding
Any interrupt conditions that occur while the The Address decode is performed by pulling known ALERT/THERM2 pin is masked wil update the Status currents from V Register normally. There are also individual channel DD through the external resistor causing the pin voltage to drop based on the masks (see Register 5-20). respective current/resistor relationship. This pin The ALERT/THERM2 pin is used as an interrupt signal voltage is compared against a threshold that or as an SMBus Alert signal that allows an SMBus determines the value of the pull-up resistor. slave to communicate an error condition to the master. The MCP9902/3/4-A SMBus slave address is deter- One or more ALERT/THERM2 Outputs can be mined by the pull-up resistor on the THERM/ADDR pin hard-wired together. as shown in Table 4-2. 4.6.2 ALERT/THERM2 PIN IN THERM
TABLE 4-2: I2C/SMBUS ADDRESS
MODE
DECODE
When the ALERT/THERM2 pin is configured to oper- ate in THERM mode, it will be asserted if any of the
Pull Up Resistor on SMBus Address
measured temperatures exceeds the respective high
THERM pin (±5%)
limit. The ALERT/THERM2 pin will remain asserted 4.7 kΩ 1111_100 (r/w)b until all temperatures drop below the corresponding 6.8 kΩ 1011_100 (r/w)b high limit minus the Therm Hysteresis value. 10 kΩ 1001_100 (r/w)b When the ALERT/THERM2 pin is asserted in THERM mode, the corresponding high limit status bits wil be 15 kΩ 1101_100 (r/w)b set. Reading these bits will not clear them until the 22 kΩ 0011_100 (r/w)b ALERT/THERM2 pin is deasserted. Once the 33 kΩ 0111_100 (r/w)b ALERT/THERM2 pin is deasserted, the status bits wil The MCP9902-1 I2C/SMBus address is hard coded to be automatically cleared. 1001_100(r/w). The MASK_ALL bit wil not block the ALERT/THERM2 The MCP9902-2 I2C/SMBus address is hard coded to pin in this mode; however, the individual channel 1001_101(r/w). masks (see Register 5-20) will prevent the respective The MCP9903-1 I2C/SMBus address is hard coded to channel from asserting the ALERT/THERM2 pin. 1001_100(r/w). 4.6.3 DEFAULT POWER UP CONDITIONS The MCP9903-2 I2C/SMBus address is hard coded to On power-up, the ALERT/THERM2 is disabled and the 1001_101(r/w). MASK ALL (MSKAL) bit in the CONFIG register (see The MCP9904-1 I2C/SMBus address is hard coded to Register 5-6) is set. Additionally, an artificial fault has 1001_100(r/w). been placed in the device, and is enabled at power up. The MCP9904-2 I2C/SMBus address is hard coded to The FAULT TEST (FT_TST) bit in the Fault Status reg- 1001_101(r/w). ister (see Register 5-20) will allow the assertion of the ALERT/THERM2 pin when this test mode is enabled once MSKAL is cleared. To use the ALERT/THERM2 functions described in this section, the MSKAL bit must be set to ‘0’, and the FT_TST bit to ‘1’ in order for the pin to function properly. DS20005382C-page 10 2015-2016 Microchip Technology Inc. Document Outline Multi-Channel Low-Temperature Remote Diode Sensor Features Typical Applications Description Package Types MCP9902/3/4 Functional Block Diagram 1.0 Electrical Characteristics 1.1 Electrical Specifications Absolute Maximum Ratings 1.2 DC Characteristics 1.3 Thermal Specifications FIGURE 1-1: POR and POR Rearm With Slow Rising VDD. 1.4 SMBUS Module Specifications FIGURE 1-2: SMBus Timing Diagram. 2.0 Typical Operating Curves FIGURE 2-1: Supply Current vs. Conversion Rate (TA = +25°C, VDD = 3.3V). FIGURE 2-2: IDD vs. Temperature. FIGURE 2-3: Temperature Error vs. Filter Capacitor (VDD = 3.3V, TA = TD = +25°C, 2N3904). FIGURE 2-4: Temperature Error vs. Ambient Temperature (VDD = 3.3V, TD = +25°C, 16 Units, 2N3904). FIGURE 2-5: Temperature Error vs. Remote Temperature. (VDD = 3.3V, TD = +25°C, 16 Units, 2N3904). FIGURE 2-6: Temperature Error vs. Series Resistance (TA = +25°C, VDD = 3.3V). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Power Supply (VDD) 3.2 Diode 1 Pair (DN1/DP1) 3.3 Diode 2 Pair (DN2/DP2) 3.4 Anti-Parallel Diode Pair (DN3/DP2 and DN2/DP3) (MCP9904 only) 3.5 THERM LIMIT ALERT (THERM/ADDR) 3.6 Ground (GND) 3.7 Maskable ALERT (ALERT/THERM2) 3.8 SMBus Data (SMDATA) 3.9 SMBus Clock (SMCLK) 3.10 Exposed Thermal Pad (EP) 4.0 Functional Description FIGURE 4-1: MCP9902/3/4 System Diagram. 4.1 Power States 4.2 Conversion Rates TABLE 4-1: Conversion Rate 4.3 Dynamic Averaging 4.4 THERM Output 4.5 THERM Pin Address Decoding TABLE 4-2: I2C/SMBus Address Decode 4.6 ALERT/THERM2 Output 4.7 Temperature Measurement 4.8 Beta Compensation 4.9 Resistance Error Correction (REC) 4.10 Programmable External Diode Ideality Factor TABLE 4-3: Ideality Factor Look-Up Table (Diode Model) TABLE 4-4: Substrate Diode Ideality Factor Look-Up Table (BJT Model) 4.11 Diode Faults 4.12 Consecutive Alerts TABLE 4-5: Consecutive Alert/ THERM Settings 4.13 Limit Register Interaction 4.14 Digital Filter TABLE 4-6: Filter Settings FIGURE 4-2: Temperature Filter Step Response. FIGURE 4-3: Temperature Filter Impulse Response. 4.15 Temperature Measurement Results and Data TABLE 4-7: Temperature Data Format 5.0 Communications Protocol 5.1 SMBus Control Bits 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus Protocols TABLE 5-1: Protocol Format TABLE 5-2: Write Byte Protocol TABLE 5-3: Read Byte Protocol TABLE 5-4: Send Byte Protocol TABLE 5-5: Receive Byte Protocol 5.5 Alert Response Address TABLE 5-6: Alert Response Address Protocol 5.6 Register Description TABLE 5-7: Register Set in Hexadecimal Order (Continued) 5.7 Data Read Interlock Register 5-1: iNT TEMP HI BYTE: Internal Diode High Byte Temperature Data Register (ADDRESS 00h) Register 5-2: INT temp LO byte: Internal Diode LOW Byte Temperature Data Register (ADDRESS 29h) Register 5-3: EXT(n) TEMP hi byte: EXTERNAL Diode High Byte Temperature Data Register (Addresses 01h, 23h, 2Ah) Register 5-4: EXT(n) TEMP Lo Byte: EXTERNAL Diode LOW Byte Temperature Data Register (Addresses 10h, 24h, 2Bh) Register 5-5: Status: status register reporting state of internal and external diodes (ADDRESS 02h) Register 5-6: CONFIG: Configuration Register (Addresses 03h and 09h) Register 5-7: CONVERT: TEMPERATURE CONVERSION RATE REGISTER (ADDRESS 04h, 0AH) Register 5-8: int diode hi limit temp: INTERNAL DIODE HIGH LIMIT TEMPERATURE REGISTER (Addresses 05h and 0Bh) Register 5-9: int diode lo lim TEMP – INTERNAL DIODE LOW LIMIT TEMPERATURE REGISTER (addresses 06H AND 0CH) Register 5-10: EXT(n) hi lim temp HB – EXTERNAL DIODE N HIGH TEMPERATURE LIMIT, high byte REGISTER (addresses 07h and 0dh, 15h, 2Ch) Register 5-11: EXT(n) hi lim LB – EXTERNAL DIODE N HIGH LIMIT TEMPERATURE, low byte REGISTER (Addresses 13H, 17h, 2eh) Register 5-12: EXT(n) lo lim HB – EXTERNAL DIODE N low LIMIT, high byte TEMPERATURE REGISTER (addresses 08h and 0eh, 16h, 2Dh) Register 5-13: EXT(N) LO lim LB – EXTERNAL DIODE N LOW LIMIT, low byte TEMPERATURE REGISTER (Addresses 14H, 18h, 2fh) Register 5-14: scrtchpd(N): sCRATCHPAD REGISTER (addresses 11H AND 12H) Register 5-15: ONE SHOT – ONE-shot temperature conversion initiation REGISTER (address 0fh) Register 5-16: EXT(n) THrm lim – external diode (N) therm limit REGISTER (addresses 19h, 1Ah and 30h) Register 5-17: iNTD THrm lim – internal diode therm limit REGISTER (address 20h) Register 5-18: THRM HYS – therm limit hysteresis REGISTER (address 21h) Register 5-19: EXT FLT STS – external diode fault status REGISTER (address 1Bh) Register 5-20: DIODE FAULT MASK – diode fault mask REGISTER (address 1Fh) Register 5-21: CONSEC ALERT – Consecutive Alert Register (address 22h) Register 5-22: ext(N) beta cfg – beta compensation configuration Register (addresses 25h and 26h) Register 5-23: ext (n) IDEALITY FACTOR – External Diode N Ideality Factor Register (addresses 27h, 28h and 31h) Register 5-24: HI LIM STS – High Limit Status Register (address 35h) Register 5-25: LO LIM STS – Low Limit Status Register (address 36h) Register 5-26: THRM LIM STS – High Limit Status Register (address 37h) Register 5-27: FLTR SEL: Filter Selection Register (address 40h) Register 5-28: PROD_ID – Product ID Register (address FDh) Register 5-29: MCHP_ID – Manufacturer ID Register (address FEh) Register 5-30: REVISION – Revision Register (address FFh) 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Revision C (July 2016) Revision B (March 2016) Revision A (December 2015) Product Identification System Trademarks Worldwide Sales and Service
