Datasheet KSZ8775CLX (Microchip) - 9
| Manufacturer | Microchip |
| Description | Integrated 5–Port 10/100 Managed Ethernet Switch with Port 4 RMII and Port 5 RGMII/MII/ RMII Interfaces |
| Pages / Page | 132 / 9 — KSZ8775CLX. TABLE 2-1:. Num Pins SIGNALS (CONTINUED). Pin Name Type Port … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
KSZ8775CLX. TABLE 2-1:. Num Pins SIGNALS (CONTINUED). Pin Name Type Port Pin Description. RMII:. Port 4 SW4-RMII receive bit [0]
Model Line for this Datasheet
Text Version of Document
KSZ8775CLX
TABLE 2-1:
Num Pins SIGNALS (CONTINUED)
Pin Name Type Port Pin Description
RMII:
Port 4 SW4-RMII receive bit [0].
Strap Option: Clock or Normal Mode Select in
Port 4 RMII 43 RXD4_0 Ipd/O 4 PU = Clock mode in RMII, using 25MHz OSC
clock and provide 50 MHz RMII clock from pin
RXC4 (Default)
PD = Normal mode in RMII, the TXC4/REFCLKI4
pin on the Port 4 RMII will receive an external
50 MHz clock
Note: Port 4 also can use either an internal or
external clock in RMII mode based on this strap
pin or the setting of the Register 70 (0x46) bit [7].
An external pull-up/down resistor is requested for
the strap-in. 44 RXDV4/CRSDV4 IPD/O 45 NC NC 46 VDD12D P 47 TXC5/REFCLKI5/
GTXC5 I/O 4 RMII:
CRSDV4 is for Port 4 RMII carrier sense/receive
data valid output.
No connect 5 1.2V core power 5 Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Input for receiving 50 MHz in normal mode.
RGMII: Input 125 MHz clock with falling and rising
edge to latch data for the data transfer. 48 RXC5/
GRXC5 I/O 5 Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Output 50 MHz reference clock for the
receiving/transmit in the clock mode.
RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving. 49 RXD5_0 IPD/O 5 RGMII/MII/RMII:
Port 5 switch receive bit [0] 50 RXD5_1 IPD/O 5 RGMII/MII/RMII:
Port 5 switch receive bit [1] 51 GNDD GND 52 VDDIO P 53 RXD5_2 2015 Microchip Technology Inc. IPD/O Digital ground
3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 5 RGMII/MII:
Port 5 switch receive bit [2]
RMII:
No connection. DS00002129C-page 9
TABLE 2-1:
Num Pins SIGNALS (CONTINUED)
Pin Name Type Port Pin Description
RMII:
Port 4 SW4-RMII receive bit [0].
Strap Option: Clock or Normal Mode Select in
Port 4 RMII 43 RXD4_0 Ipd/O 4 PU = Clock mode in RMII, using 25MHz OSC
clock and provide 50 MHz RMII clock from pin
RXC4 (Default)
PD = Normal mode in RMII, the TXC4/REFCLKI4
pin on the Port 4 RMII will receive an external
50 MHz clock
Note: Port 4 also can use either an internal or
external clock in RMII mode based on this strap
pin or the setting of the Register 70 (0x46) bit [7].
An external pull-up/down resistor is requested for
the strap-in. 44 RXDV4/CRSDV4 IPD/O 45 NC NC 46 VDD12D P 47 TXC5/REFCLKI5/
GTXC5 I/O 4 RMII:
CRSDV4 is for Port 4 RMII carrier sense/receive
data valid output.
No connect 5 1.2V core power 5 Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Input for receiving 50 MHz in normal mode.
RGMII: Input 125 MHz clock with falling and rising
edge to latch data for the data transfer. 48 RXC5/
GRXC5 I/O 5 Port 5 Switch GMAC5 Clock Pin:
MII: 2.5/25 MHz clock, PHY mode is output, MAC
mode is input.
RMII: Output 50 MHz reference clock for the
receiving/transmit in the clock mode.
RGMII: Output 125 MHz clock with falling and rising edge to latch data for the receiving. 49 RXD5_0 IPD/O 5 RGMII/MII/RMII:
Port 5 switch receive bit [0] 50 RXD5_1 IPD/O 5 RGMII/MII/RMII:
Port 5 switch receive bit [1] 51 GNDD GND 52 VDDIO P 53 RXD5_2 2015 Microchip Technology Inc. IPD/O Digital ground
3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 5 RGMII/MII:
Port 5 switch receive bit [2]
RMII:
No connection. DS00002129C-page 9
