Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 8

KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
MLL/FLL: Switch MII receive clock. Output in PHY MII mode 36 SMRXC3/NC I/O Input in MAC MII mode RLL: No Connection. 37 GND GND Digital ground 38 VDDC P 1.8V digital core power input from VDDCO (pin 56). SPI slave mode: serial data output Note: an external pull-up is needed on this pin when it is in use. 39 SPIQ Ipu/O
Strap option:
XCLK Frequency Selection PU = 25 MHz PD = 50 MHz SPI slave mode: chip select (active-low) When SPISN is high, the KSZ8873MLL/FLL/RLL is deselected and SPIQ is 40 SPISN Ipu held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. Note: an external pull-up is needed on this pin when it is in use. Interrupt 41 INTRN Opu Active-low signal to host CPU to indicate an interrupt status bit is set when lost link. Refer to register 187 and 188. SPI slave mode/I2C slave mode: clock input 42 SCL_MDC I/O I2C master mode: clock output MIIM clock input SPI slave mode: serial data input I2C master/slave mode: serial data input/output 43 SDA_MDIO Ipu/O MIIM: data input/output Note: an external pull-up is needed on this pin when it is in use. Unused pin, only this NC pin can be pulled down by a pull-down resistor for 44 NC NC better EMI. PU = enable auto-negotiation on port 1 45 P1ANEN Ipu/O PD = disable auto-negotiation on port 1 PU = force port 1 to 100BT if P1ANEN = 0 46 P1SPD Ipu/O PD = force port 1 to 10BT if P1ANEN = 0 PU = port 1 default to full-duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0. 47 P1DPX Ipu/O PD = port 1 default to half-duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in half-duplex mode if P1ANEN = 0. 48 GND GND Digital ground 49 VDDC P 1.8V digital core power input from VDDCO (Pin 56). PU = always enable (force) port 1 flow control feature 50 P1FFC Ipu/O PD = port 1 flow control feature enable is determined by auto-negotiation result. DS00002348A-page 8

 2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service