Datasheet LTC3723 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Synchronous Push-Pull PWM Controllers |
| Pages / Page | 20 / 6 — PI DESCRIPTIO S (LTC3723-1/LTC3723-2). VREF (Pin 1/Pin 1):. CT (Pin 8/Pin … |
| File Format / Size | PDF / 347 Kb |
| Document Language | English |
PI DESCRIPTIO S (LTC3723-1/LTC3723-2). VREF (Pin 1/Pin 1):. CT (Pin 8/Pin 8):. SDRB (Pin 2/Pin 2):. SDRA (Pin 3/Pin 3):
Model Line for this Datasheet
Text Version of Document
LTC3723-1/LTC3723-2
U U PI DESCRIPTIO S (LTC3723-1/LTC3723-2) VREF (Pin 1/Pin 1):
Output of the 5.0V Reference. VREF is mended. VIN and VREF bypass capacitors must be termi- capable of supplying up to 18mA to external circuitry. VREF nated with a star configuration as close to GND as practical should be decoupled to GND with a 0.47µF ceramic for best performance. capacitor.
CT (Pin 8/Pin 8):
Timing Capacitor for the Oscillator. Use
SDRB (Pin 2/Pin 2):
50mA Driver for Synchronous Recti- a ±5% or better low ESR ceramic capacitor for best fier associated with DRVB. results. CT ramp amplitude is 2.35V peak-to-peak (typical).
SDRA (Pin 3/Pin 3):
50mA Driver for Synchronous Recti- fier associated with DRVA.
DPRG (Pin 9/Pin 12):
Programming Input for Push-Pull Dead-Time. Connect a resistor between DPRG and V
DRVB (Pin 4/Pin 4):
High Speed 1.5A Sink, 1A Source REF to program the dead-time. The nominal voltage on DPRG Totem Pole MOSFET Driver. Connect to gate of external is 2V. push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor
RAMP (N/A/Pin 9):
Input to PWM Comparator for connected between DRVA and the MOSFET gate is op- LTC3723-2 Only (Voltage Mode Controller). The voltage tional and will improve the gate drive signal quality if the on RAMP is internally level shifted by 650mV. PCB trace from the driver to the MOSFET cannot be made
CS (Pin 10/Pin 10):
Input to Pulse-by-Pulse and Overload short. Current Limit Comparators, Output of Slope Compensa-
VCC (Pin 5/Pin 5):
Supply Voltage Input to the LTC3723-1/ tion Circuitry. The pulse-by-pulse comparator has a nomi- LTC3723-2 and 10.25V Shunt Regulator. The chip is nal 300mV threshold, while the overload comparator has enabled after VCC has risen high enough to allow the VCC a nominal 600mV threshold. An internal switch discharges shunt regulator to conduct current and the UVLO com- CS to GND after every timing period. Slope compensation parator threshold is exceeded. Once the VCC shunt regu- current flows out of CS during the PWM period. lator has turned on, VCC can drop to as low as 6V (typical) An external resistor connected from CS to the external and maintain operation. Bypass VCC to GND with a high current sense resistor programs the amount of slope quality 1µF or larger ceramic capacitor to supply the compensation. transient currents caused by the high speed switching and
COMP (Pin 11/Pin 11):
Error Amplifier Output, Inverting capacitive loads presented by the on chip totem pole Input to Phase Modulator. drivers.
R DRVA (Pin 6/Pin 6):
High Speed 1.5A Sink, 1A Source
LEB (Pin 12/N/A):
Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor connected between Totem Pole MOSFET Driver. Connect to gate of external R push-pull MOSFET with as short a PCB trace as practical LEB and GND to program from 40ns to 310ns of leading edge blanking of the current sense signal on CS for the to preserve drive signal integrity. A low value resistor LTC3723-1. A ±1% tolerance resistor is recommended. connected between DRVA and the MOSFET gate is op- The LTC3723-2 has a fixed blanking time of approximately tional and will improve the gate drive signal quality if the 80ns. The nominal voltage on R PCB trace from the driver to the MOSFET cannot be made LEB is 2V. If leading edge blanking is not required, tie R short. LEB to VREF to disable.
FB (Pin 13/Pin 13):
Error Amplifier Inverting Input. This is
GND (Pin 7/Pin 7):
All circuits in the LTC3723 are refer- the voltage feedback input for the LTC3723. The nominal enced to GND. Use of a ground plane is highly recom- regulation voltage at FB is 1.2V. 372312f 6
U U PI DESCRIPTIO S (LTC3723-1/LTC3723-2) VREF (Pin 1/Pin 1):
Output of the 5.0V Reference. VREF is mended. VIN and VREF bypass capacitors must be termi- capable of supplying up to 18mA to external circuitry. VREF nated with a star configuration as close to GND as practical should be decoupled to GND with a 0.47µF ceramic for best performance. capacitor.
CT (Pin 8/Pin 8):
Timing Capacitor for the Oscillator. Use
SDRB (Pin 2/Pin 2):
50mA Driver for Synchronous Recti- a ±5% or better low ESR ceramic capacitor for best fier associated with DRVB. results. CT ramp amplitude is 2.35V peak-to-peak (typical).
SDRA (Pin 3/Pin 3):
50mA Driver for Synchronous Recti- fier associated with DRVA.
DPRG (Pin 9/Pin 12):
Programming Input for Push-Pull Dead-Time. Connect a resistor between DPRG and V
DRVB (Pin 4/Pin 4):
High Speed 1.5A Sink, 1A Source REF to program the dead-time. The nominal voltage on DPRG Totem Pole MOSFET Driver. Connect to gate of external is 2V. push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor
RAMP (N/A/Pin 9):
Input to PWM Comparator for connected between DRVA and the MOSFET gate is op- LTC3723-2 Only (Voltage Mode Controller). The voltage tional and will improve the gate drive signal quality if the on RAMP is internally level shifted by 650mV. PCB trace from the driver to the MOSFET cannot be made
CS (Pin 10/Pin 10):
Input to Pulse-by-Pulse and Overload short. Current Limit Comparators, Output of Slope Compensa-
VCC (Pin 5/Pin 5):
Supply Voltage Input to the LTC3723-1/ tion Circuitry. The pulse-by-pulse comparator has a nomi- LTC3723-2 and 10.25V Shunt Regulator. The chip is nal 300mV threshold, while the overload comparator has enabled after VCC has risen high enough to allow the VCC a nominal 600mV threshold. An internal switch discharges shunt regulator to conduct current and the UVLO com- CS to GND after every timing period. Slope compensation parator threshold is exceeded. Once the VCC shunt regu- current flows out of CS during the PWM period. lator has turned on, VCC can drop to as low as 6V (typical) An external resistor connected from CS to the external and maintain operation. Bypass VCC to GND with a high current sense resistor programs the amount of slope quality 1µF or larger ceramic capacitor to supply the compensation. transient currents caused by the high speed switching and
COMP (Pin 11/Pin 11):
Error Amplifier Output, Inverting capacitive loads presented by the on chip totem pole Input to Phase Modulator. drivers.
R DRVA (Pin 6/Pin 6):
High Speed 1.5A Sink, 1A Source
LEB (Pin 12/N/A):
Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor connected between Totem Pole MOSFET Driver. Connect to gate of external R push-pull MOSFET with as short a PCB trace as practical LEB and GND to program from 40ns to 310ns of leading edge blanking of the current sense signal on CS for the to preserve drive signal integrity. A low value resistor LTC3723-1. A ±1% tolerance resistor is recommended. connected between DRVA and the MOSFET gate is op- The LTC3723-2 has a fixed blanking time of approximately tional and will improve the gate drive signal quality if the 80ns. The nominal voltage on R PCB trace from the driver to the MOSFET cannot be made LEB is 2V. If leading edge blanking is not required, tie R short. LEB to VREF to disable.
FB (Pin 13/Pin 13):
Error Amplifier Inverting Input. This is
GND (Pin 7/Pin 7):
All circuits in the LTC3723 are refer- the voltage feedback input for the LTC3723. The nominal enced to GND. Use of a ground plane is highly recom- regulation voltage at FB is 1.2V. 372312f 6
