Datasheet ATtiny26, ATtiny26L (Atmel) - 3
| Manufacturer | Atmel |
| Pages / Page | 182 / 3 — ATtiny26(L). Description |
| File Format / Size | PDF / 3.1 Mb |
| Document Language | English |
ATtiny26(L). Description
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ATtiny26(L) Description
The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchro- nous rectification. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications. The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, program- mable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next inter- rupt or hardware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.
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1477K–AVR–08/10 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND AVCC Port A (PA7..PA0) Port B (PB7..PB0) XTAL1 XTAL2 General Information Resources Code Examples AVR CPU Core Architectural Overview General Purpose Register File X-register, Y-register, and Z-register ALU – Arithmetic Logic Unit Status Register – SREG Stack Pointer – SP Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memories In-System Programmable Flash Program Memory SRAM Data Memory EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH ADC Clock – clkADC Internal PLL for Fast Peripheral Clock Generation – clkPCK Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock High Frequency PLL Clock – PLLCLK System Control and Reset Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode ADC Noise Reduction Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Alternate Port Functions MCU Control Register – MCUCR Alternate Functions of Port A Alternate Functions Of Port B Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Interrupts Interrupt Vectors Interrupt Handling Interrupt Response Time General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupt Pin Change Interrupt Timer/Counters Timer/Counter0 Prescaler Timer/Counter1 Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 8-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1 Timer/Counter1 Output Compare RegisterA – OCR1A Timer/Counter1 Output Compare RegisterB – OCR1B Timer/Counter1 Output Compare RegisterC – OCR1C PLL Control and Status Register – PLLCSR Timer/Counter1 Initialization for Asynchronous Mode Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR Universal Serial Interface – USI Overview Register Descriptions USI Data Register – USIDR USI Status Register – USISR USI Control Register – USICR Functional Descriptions Three-wire Mode SPI Master Operation Example SPI Slave Operation Example Two-wire Mode Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt Analog Comparator Analog Comparator Control and Status Register – ACSR Analog to Digital Converter Features Operation Prescaling and Conversion Timing Changing Channel or Reference Selection ADC Noise Canceler Function ADC Conversion Result ADC Multiplexer Selection Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise Canceling Techniques Offset Compensation Schemes Memory Programming Program and Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive ADC Characteristics ATtiny26 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 20P3 20S 32M1-A Errata ATtiny26 Rev. B/C/D Datasheet Revision History Rev. 1477K-08/10 Rev. 1477J-06/07 Rev. 1477I-05/06 Rev. 1477H-04/06 Rev. 1477G-03/05 Rev. 1477F-12/04 Rev. 1477E-10/03 Rev. 1477D-05/03 Rev. 1477C-09/02 Rev. 1477B-04/02 Rev. 1477A-03/02 Table of Contents
The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchro- nous rectification. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications. The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, program- mable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next inter- rupt or hardware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.
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1477K–AVR–08/10 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND AVCC Port A (PA7..PA0) Port B (PB7..PB0) XTAL1 XTAL2 General Information Resources Code Examples AVR CPU Core Architectural Overview General Purpose Register File X-register, Y-register, and Z-register ALU – Arithmetic Logic Unit Status Register – SREG Stack Pointer – SP Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memories In-System Programmable Flash Program Memory SRAM Data Memory EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH ADC Clock – clkADC Internal PLL for Fast Peripheral Clock Generation – clkPCK Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock High Frequency PLL Clock – PLLCLK System Control and Reset Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode ADC Noise Reduction Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Alternate Port Functions MCU Control Register – MCUCR Alternate Functions of Port A Alternate Functions Of Port B Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Interrupts Interrupt Vectors Interrupt Handling Interrupt Response Time General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupt Pin Change Interrupt Timer/Counters Timer/Counter0 Prescaler Timer/Counter1 Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 8-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1 Timer/Counter1 Output Compare RegisterA – OCR1A Timer/Counter1 Output Compare RegisterB – OCR1B Timer/Counter1 Output Compare RegisterC – OCR1C PLL Control and Status Register – PLLCSR Timer/Counter1 Initialization for Asynchronous Mode Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR Universal Serial Interface – USI Overview Register Descriptions USI Data Register – USIDR USI Status Register – USISR USI Control Register – USICR Functional Descriptions Three-wire Mode SPI Master Operation Example SPI Slave Operation Example Two-wire Mode Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt Analog Comparator Analog Comparator Control and Status Register – ACSR Analog to Digital Converter Features Operation Prescaling and Conversion Timing Changing Channel or Reference Selection ADC Noise Canceler Function ADC Conversion Result ADC Multiplexer Selection Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise Canceling Techniques Offset Compensation Schemes Memory Programming Program and Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive ADC Characteristics ATtiny26 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 20P3 20S 32M1-A Errata ATtiny26 Rev. B/C/D Datasheet Revision History Rev. 1477K-08/10 Rev. 1477J-06/07 Rev. 1477I-05/06 Rev. 1477H-04/06 Rev. 1477G-03/05 Rev. 1477F-12/04 Rev. 1477E-10/03 Rev. 1477D-05/03 Rev. 1477C-09/02 Rev. 1477B-04/02 Rev. 1477A-03/02 Table of Contents
