Datasheet ATtiny22, ATtiny22L - Preliminary (Atmel) - 10
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 2K Bytes of In-System Programmable Flash |
| Pages / Page | 59 / 10 — I/O Direct. Figure 10. Data Direct. Figure 11. ATtiny22/22L |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
I/O Direct. Figure 10. Data Direct. Figure 11. ATtiny22/22L
Model Line for this Datasheet
Text Version of Document
I/O Direct Figure 10.
I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct Figure 11.
Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.
10 ATtiny22/22L
Document Outline Features Description Block Diagram Pin Descriptions ATtiny22/L VCC GND Port B (PB4..PB0) RESET CLOCK Clock Options External Clock Architectural Overview General Purpose Register File X-Register, Y-Register, and Z-Register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory EEPROM Data Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect With Pre-Decrement Data Indirect With Post-Increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memory Access and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SPL Reset and Interrupt Handling Reset Sources Power-On Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt FLAG Register - TIFR External Interrupt Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Timer/Counter Timer/Counter Prescaler 8-Bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEAR EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption I/O Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB General Digital I/O Alternate Functions of Port B CLOCK - Port B, Bit 3 SCK/T0 - Port B, Bit 2 MISO - Port B, Bit 1 MOSI - Port B, Bit 0 Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM High-Voltage Serial Programming High-Voltage Serial Programming Algorithm High-Voltage Serial Programming Characteristics Low-Voltage Serial Downloading Low-Voltage Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Low-Voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Typical characteristics Register Summary Instruction Set Summary (Continued) Ordering Information
I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct Figure 11.
Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.
10 ATtiny22/22L
Document Outline Features Description Block Diagram Pin Descriptions ATtiny22/L VCC GND Port B (PB4..PB0) RESET CLOCK Clock Options External Clock Architectural Overview General Purpose Register File X-Register, Y-Register, and Z-Register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory EEPROM Data Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect With Pre-Decrement Data Indirect With Post-Increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memory Access and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SPL Reset and Interrupt Handling Reset Sources Power-On Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt FLAG Register - TIFR External Interrupt Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Timer/Counter Timer/Counter Prescaler 8-Bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEAR EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption I/O Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB General Digital I/O Alternate Functions of Port B CLOCK - Port B, Bit 3 SCK/T0 - Port B, Bit 2 MISO - Port B, Bit 1 MOSI - Port B, Bit 0 Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM High-Voltage Serial Programming High-Voltage Serial Programming Algorithm High-Voltage Serial Programming Characteristics Low-Voltage Serial Downloading Low-Voltage Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Low-Voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Typical characteristics Register Summary Instruction Set Summary (Continued) Ordering Information
