Datasheet LTM4634 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Triple Output 5A/5A/4A Step-Down DC/DC μModule (Power Module) Regulator |
| Pages / Page | 32 / 8 — pin FuncTions. INTVCC (J8):. RUN1, RUN2, RUN3 (L10, L11, K11):. SGND … |
| File Format / Size | PDF / 759 Kb |
| Document Language | English |
pin FuncTions. INTVCC (J8):. RUN1, RUN2, RUN3 (L10, L11, K11):. SGND (K6-K7, L6-L7):. PGOOD12, PGOOD3 (M2, M3):
Model Line for this Datasheet
Text Version of Document
LTM4634
pin FuncTions INTVCC (J8):
Output of the Internal Bias LDO for Powering
RUN1, RUN2, RUN3 (L10, L11, K11):
Run Control Inputs. Internal Control Circuitry. Connect a 4.7µF ceramic capaci- A voltage above 1.3V on any RUN pin turns on that par- tor to ground for decoupling. If the voltage at CNTL_PWR ticular channel. However, forcing any of these RUN pins is ≤5.8V, tie the INTVCC pin to CNTL_PWR for optimum below 1.15V causes that channel to shut down. Each of efficiency. If the voltage at CNTL_PWR is >5.8V, leave the RUN pins has an internal 10k resistor to ground. This INTVCC floating. See the Applications Information section. resistor can be used with an external pull-up resistor to
SGND (K6-K7, L6-L7):
Signal Ground Connections. The the input voltage to set a UVLO for that channel, or simply signal ground connection in the module is separated from to turn on the channel. The RUN pins have a maximum normal power ground (GND) by an internal 2.2Ω resistor. voltage of 6V. See the Applications Information section. This allows the designer to connect the signal ground pin
PGOOD12, PGOOD3 (M2, M3):
Output Voltage Power close to GND near the external output capacitors on the Good Indicator for VOUT1 and VOUT2 Combined, and VOUT3 regulator channel’s outputs. The entire internal small-signal Separate. The open-drain logic output is pulled to ground feedback circuitry is referenced to SGND, thus allowing when the output voltage is not within ±7.5% of the regula- for better output regulation. See the recommended layout tion point. in the Applications Information section.
COMP1, COMP2, COMP3 (M4, L4, K4):
Current Control
EXTVCC (L3):
External Bias Power Input. The internal bias Threshold and Error Amplifier Compensation Point. The LDO is bypassed whenever the voltage at EXTVCC is above current comparator threshold increases with this control 4.7V. Never exceed 6V at this pin and ensure CNTL_PWR > voltage. The LTM4634 regulator channels are all internally EXTVCC at all times to avoid reverse polarity on the internal compensated for proper stability. COMP1 and COMP2 can bias LDO. Connect a 1µF capacitor to ground when used be tied together for PolyPhase 10A parallel operation. See otherwise leave floating. Use a 5V bias or 5V output to the Applications Information section. power this pin to improve efficiency.
VFB1, VFB2, VFB3 (M5, L5, K5):
The Negative Input of the
FREQ/PLLLPF (L8):
Frequency Set and PLL Lowpass Filter Error Amplifier for Each of the Three Channels. Internally, Pin. This pin is driven with a DC voltage to set the oper- each of these pins is connected to their respective output ating frequency. The recommended operating frequency with a 60.4k precision resistor. Different output voltages will be supplied in the efficiency graphs for optimal per- can be programmed with an additional resistor between formance. A specific frequency can be chosen as long as each individual VFB pin and ground. In PolyPhase operation, the minimum on-time is not violated, and inductor ripple tying the VFB1 and VFB2 pins together allows for parallel current is optimized. When an external clock is used, then operation up to 10A. See the Applications Information the FREQ/PLLLPF pin must not be connected to any DC section for details. voltage. The pin must be floating and will have the proper
TK/SS1, TK/SS2, TK/SS3 (M9, M10, M11):
Output Voltage internal compensation for the internal loop filter. See the Tracking and Soft-Start Inputs. When one particular channel Applications Information section. is configured to be the master, a capacitor to ground at
MODE/PLLIN (L9):
Forced Continuous Mode, Burst Mode, this pin sets the ramp rate for the master channel’s output or Pulse-Skipping Mode Selection Pin and External Syn- voltage. When the channel is configured to be the slave, chronization Input to Phase Detector Pin. Connect this pin the VFB voltage of the master channel is reproduced by a to SGND to force all channels into the continuous mode resistor divider and applied to this pin. Internal soft-start of operation. Connect to INTVCC to enable pulse-skipping currents of 1.5μA are charging the soft-start capacitors. mode of operation. Leave floating to enable Burst Mode In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to operation. A clock on the pin will force the controller into be shorted externally. continuous mode of operation and synchronize the internal oscillator. See the Applications Information section. 4634f 8 For more information www.linear.com/LTM4634 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Related Parts
pin FuncTions INTVCC (J8):
Output of the Internal Bias LDO for Powering
RUN1, RUN2, RUN3 (L10, L11, K11):
Run Control Inputs. Internal Control Circuitry. Connect a 4.7µF ceramic capaci- A voltage above 1.3V on any RUN pin turns on that par- tor to ground for decoupling. If the voltage at CNTL_PWR ticular channel. However, forcing any of these RUN pins is ≤5.8V, tie the INTVCC pin to CNTL_PWR for optimum below 1.15V causes that channel to shut down. Each of efficiency. If the voltage at CNTL_PWR is >5.8V, leave the RUN pins has an internal 10k resistor to ground. This INTVCC floating. See the Applications Information section. resistor can be used with an external pull-up resistor to
SGND (K6-K7, L6-L7):
Signal Ground Connections. The the input voltage to set a UVLO for that channel, or simply signal ground connection in the module is separated from to turn on the channel. The RUN pins have a maximum normal power ground (GND) by an internal 2.2Ω resistor. voltage of 6V. See the Applications Information section. This allows the designer to connect the signal ground pin
PGOOD12, PGOOD3 (M2, M3):
Output Voltage Power close to GND near the external output capacitors on the Good Indicator for VOUT1 and VOUT2 Combined, and VOUT3 regulator channel’s outputs. The entire internal small-signal Separate. The open-drain logic output is pulled to ground feedback circuitry is referenced to SGND, thus allowing when the output voltage is not within ±7.5% of the regula- for better output regulation. See the recommended layout tion point. in the Applications Information section.
COMP1, COMP2, COMP3 (M4, L4, K4):
Current Control
EXTVCC (L3):
External Bias Power Input. The internal bias Threshold and Error Amplifier Compensation Point. The LDO is bypassed whenever the voltage at EXTVCC is above current comparator threshold increases with this control 4.7V. Never exceed 6V at this pin and ensure CNTL_PWR > voltage. The LTM4634 regulator channels are all internally EXTVCC at all times to avoid reverse polarity on the internal compensated for proper stability. COMP1 and COMP2 can bias LDO. Connect a 1µF capacitor to ground when used be tied together for PolyPhase 10A parallel operation. See otherwise leave floating. Use a 5V bias or 5V output to the Applications Information section. power this pin to improve efficiency.
VFB1, VFB2, VFB3 (M5, L5, K5):
The Negative Input of the
FREQ/PLLLPF (L8):
Frequency Set and PLL Lowpass Filter Error Amplifier for Each of the Three Channels. Internally, Pin. This pin is driven with a DC voltage to set the oper- each of these pins is connected to their respective output ating frequency. The recommended operating frequency with a 60.4k precision resistor. Different output voltages will be supplied in the efficiency graphs for optimal per- can be programmed with an additional resistor between formance. A specific frequency can be chosen as long as each individual VFB pin and ground. In PolyPhase operation, the minimum on-time is not violated, and inductor ripple tying the VFB1 and VFB2 pins together allows for parallel current is optimized. When an external clock is used, then operation up to 10A. See the Applications Information the FREQ/PLLLPF pin must not be connected to any DC section for details. voltage. The pin must be floating and will have the proper
TK/SS1, TK/SS2, TK/SS3 (M9, M10, M11):
Output Voltage internal compensation for the internal loop filter. See the Tracking and Soft-Start Inputs. When one particular channel Applications Information section. is configured to be the master, a capacitor to ground at
MODE/PLLIN (L9):
Forced Continuous Mode, Burst Mode, this pin sets the ramp rate for the master channel’s output or Pulse-Skipping Mode Selection Pin and External Syn- voltage. When the channel is configured to be the slave, chronization Input to Phase Detector Pin. Connect this pin the VFB voltage of the master channel is reproduced by a to SGND to force all channels into the continuous mode resistor divider and applied to this pin. Internal soft-start of operation. Connect to INTVCC to enable pulse-skipping currents of 1.5μA are charging the soft-start capacitors. mode of operation. Leave floating to enable Burst Mode In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to operation. A clock on the pin will force the controller into be shorted externally. continuous mode of operation and synchronize the internal oscillator. See the Applications Information section. 4634f 8 For more information www.linear.com/LTM4634 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Related Parts
