Datasheet LTC4361-1, LTC4361-2 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Overvoltage/Overcurrent Protection Controller |
| Pages / Page | 16 / 5 — PIN FUNCTIONS Exposed Pad (DFN):. IN:. GATE:. ON:. GATEP:. OUT:. PWRGD:. … |
| Revision | C |
| File Format / Size | PDF / 628 Kb |
| Document Language | English |
PIN FUNCTIONS Exposed Pad (DFN):. IN:. GATE:. ON:. GATEP:. OUT:. PWRGD:. GND:. SENSE:
Model Line for this Datasheet
- LTC4361CDC-1#PBF LTC4361CDC-1#TRMPBF LTC4361CDC-1#TRPBF LTC4361CDC-2#PBF LTC4361CDC-2#TRMPBF LTC4361CDC-2#TRPBF LTC4361CTS8-1#PBF LTC4361CTS8-1#TRMPBF LTC4361CTS8-1#TRPBF LTC4361CTS8-2#PBF LTC4361CTS8-2#TRMPBF LTC4361CTS8-2#TRPBF LTC4361HDC-1#PBF LTC4361HDC-1#TRMPBF LTC4361HDC-1#TRPBF LTC4361HDC-2#PBF LTC4361HDC-2#TRMPBF LTC4361HDC-2#TRPBF LTC4361HTS8-1#PBF LTC4361HTS8-1#TRMPBF LTC4361HTS8-1#TRPBF LTC4361HTS8-2#PBF LTC4361HTS8-2#TRMPBF LTC4361HTS8-2#TRPBF LTC4361IDC-1#PBF LTC4361IDC-1#TRMPBF LTC4361IDC-1#TRPBF LTC4361IDC-2#PBF LTC4361IDC-2#TRMPBF LTC4361IDC-2#TRPBF LTC4361ITS8-1#PBF LTC4361ITS8-1#TRMPBF LTC4361ITS8-1#TRPBF LTC4361ITS8-2#PBF LTC4361ITS8-2#TRMPBF LTC4361ITS8-2#TRPBF
Text Version of Document
LTC4361-1/LTC4361-2
PIN FUNCTIONS Exposed Pad (DFN):
Ground. Connection to PCB is
IN:
Supply Voltage Input. Connect this pin to the input optional. power supply. This pin has an overvoltage threshold of
GATE:
Gate Drive for External N-Channel MOSFET. An 5.8V. After an overvoltage event, this pin must fall below internal charge pump provides a 10µA pull-up current VIN(OV) – ∆VOV to release the overvoltage lockout. During to charge the gate of the external N-channel MOSFET. An lockout, GATE is held low and the PWRGD pull-down additional ramp circuit limits the GATE ramp rate when releases. turning on to 3V/ms. For slower ramp rates, connect an
ON:
On Control Input. A logic low at ON enables the external capacitor from GATE to GND. An internal clamp LTC4361. A logic high at ON activates a low current pull- limits GATE to 6V above the OUT pin voltage. An internal down at the GATE pin and causes the LTC4361 to enter GATE high comparator controls the PWRGD pin. a low current sleep mode. An internal 5µA current pulls
GATEP:
Gate Drive for External P-Channel MOSFET. GATEP ON down to ground. Connect to ground or leave open if connects to the gate of an optional external P-channel unused. MOSFET to protect against negative voltages at IN. This
OUT:
Output Voltage Sense Input for GATE Clamp. Connect pin is internally clamped to 5.8V below VIN. An internal to the source of the external N-channel MOSFET to sense 2M resistor connects this pin to ground. Connect to IN the output voltage for GATE to OUT clamp. if not used.
PWRGD:
Power Good Status. Open-drain output with
GND:
Device Ground. internal 500k resistive pull-up to OUT. Pulls low 65ms after GATE ramps above VGATE(TH).
SENSE:
Current Sense Input. Connect a sense resistor between IN and SENSE. An overcurrent protection circuit turns off the N-channel MOSFET when the voltage across the sense resistor exceeds 50mV for more than 10µs. Rev C For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS Exposed Pad (DFN):
Ground. Connection to PCB is
IN:
Supply Voltage Input. Connect this pin to the input optional. power supply. This pin has an overvoltage threshold of
GATE:
Gate Drive for External N-Channel MOSFET. An 5.8V. After an overvoltage event, this pin must fall below internal charge pump provides a 10µA pull-up current VIN(OV) – ∆VOV to release the overvoltage lockout. During to charge the gate of the external N-channel MOSFET. An lockout, GATE is held low and the PWRGD pull-down additional ramp circuit limits the GATE ramp rate when releases. turning on to 3V/ms. For slower ramp rates, connect an
ON:
On Control Input. A logic low at ON enables the external capacitor from GATE to GND. An internal clamp LTC4361. A logic high at ON activates a low current pull- limits GATE to 6V above the OUT pin voltage. An internal down at the GATE pin and causes the LTC4361 to enter GATE high comparator controls the PWRGD pin. a low current sleep mode. An internal 5µA current pulls
GATEP:
Gate Drive for External P-Channel MOSFET. GATEP ON down to ground. Connect to ground or leave open if connects to the gate of an optional external P-channel unused. MOSFET to protect against negative voltages at IN. This
OUT:
Output Voltage Sense Input for GATE Clamp. Connect pin is internally clamped to 5.8V below VIN. An internal to the source of the external N-channel MOSFET to sense 2M resistor connects this pin to ground. Connect to IN the output voltage for GATE to OUT clamp. if not used.
PWRGD:
Power Good Status. Open-drain output with
GND:
Device Ground. internal 500k resistive pull-up to OUT. Pulls low 65ms after GATE ramps above VGATE(TH).
SENSE:
Current Sense Input. Connect a sense resistor between IN and SENSE. An overcurrent protection circuit turns off the N-channel MOSFET when the voltage across the sense resistor exceeds 50mV for more than 10µs. Rev C For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
