Datasheet ADE7953 (Analog Devices) - 4

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ADE7953 Data Sheet SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, Register Address 0x120 set to 0x30, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
PHASE ERROR BETWEEN CHANNELS Line frequency = 45 Hz to 65 Hz, HPF on Power Factor = 0.8 Capacitive ±0.05 Degrees Phase lead 37° Power Factor = 0.5 Inductive ±0.05 Degrees Phase lag 60° ACTIVE ENERGY MEASUREMENT Active Energy Measurement Error 0.1 % Over a dynamic range of 3000:1, PGA = 1, (Current Channel A) PGA = 22, integrator off Active Energy Measurement Error 0.1 % Over a dynamic range of 1000:1, PGA = 1, (Current Channel B) PGA = 16, integrator off AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz Output Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth 1.23 kHz −3 db REACTIVE ENERGY MEASUREMENT Reactive Energy Measurement Error 0.1 % Over a dynamic range of 3000:1, PGA = 1, (Current Channel A) PGA = 22, integrator off Reactive Energy Measurement Error 0.1 % Over a dynamic range of 1000:1, PGA = 1, (Current Channel B) PGA = 16, integrator off AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz Output Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 % Reactive Energy Measurement 1.23 kHz −3 db Bandwidth RMS MEASUREMENT IRMS and VRMS Measurement 1.23 kHz Bandwidth IRMS (Current Channel A) Measurement 0.2 % Over a dynamic range of 1000:1, PGA = 1, Error PGA = 22, integrator off IRMS (Current Channel B) and VRMS 0.2 % Over a dynamic range of 500:1, PGA = 1, Measurement Error PGA = 16, integrator off ANALOG INPUTS Maximum Signal Levels ±500 mV peak Differential inputs: IAP to IAN, IBP to IBN ±500 mV peak Single-ended input: VP to VN, IBP to IBN ±250 mV peak Single-ended input: IAP to IAN Input Impedance (DC) IAP Pin 50 MΩ IAN Pin 50 MΩ IBP, IBN, VP, VN Pins 540 kΩ ADC Offset Error Uncalibrated error (see the Terminology section) Current Channel B, Voltage Channel 0 ±10 mV Current Channel A −12 mV PGA = 1 −1 mV PGA = 16, PGA = 22 Gain Error External 1.2 V reference Current Channel A ±3 % Current Channel B ±3 % Voltage Channel ±3 % Rev. C | Page 4 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS SPI Interface Timing SPI Interface Timing Diagram I2C Interface Timing I2C Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY ADE7953 POWER-UP PROCEDURE REQUIRED REGISTER SETTING THEORY OF OPERATION ANALOG INPUTS Current Channel A Current Channel B Voltage Channel ANALOG-TO-DIGITAL CONVERSION Oversampling Noise Shaping Antialiasing Filter CURRENT CHANNEL ADCS di/dt Current Sensor and Digital Integrator VOLTAGE CHANNEL ADC REFERENCE CIRCUIT ROOT MEAN SQUARE MEASUREMENT CURRENT CHANNEL RMS CALCULATION VOLTAGE CHANNEL RMS CALCULATION ACTIVE POWER CALCULATION SIGN OF ACTIVE POWER CALCULATION ACTIVE ENERGY CALCULATION Active Energy Integration Time Under Steady Load Active Energy Line Cycle Accumulation Mode ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Positive-Only Accumulation Mode Absolute Accumulation Mode REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load Reactive Energy Line Cycle Accumulation Mode REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Antitamper Accumulation Mode Absolute Accumulation Mode APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load Apparent Energy Line Cycle Accumulation Mode AMPERE-HOUR ACCUMULATION ENERGY-TO-FREQUENCY CONVERSION PULSE OUTPUT CHARACTERISTICS ENERGY CALIBRATION GAIN CALIBRATION Current Channel Gain Adjustment PHASE CALIBRATION OFFSET CALIBRATION Power Offsets RMS Offsets PERIOD MEASUREMENT INSTANTANEOUS POWERS AND WAVEFORM SAMPLING POWER FACTOR USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR POWER FACTOR WITH NO-LOAD DETECTION ANGLE MEASUREMENT NO-LOAD DETECTION SETTING THE NO-LOAD THRESHOLDS ACTIVE ENERGY NO-LOAD DETECTION Active Energy No-Load Interrupt Active Energy No-Load Status Bits REACTIVE ENERGY NO-LOAD DETECTION Reactive Energy No-Load Interrupt Reactive Energy No-Load Status Bits APPARENT ENERGY NO-LOAD DETECTION Apparent Energy No-Load Interrupt Apparent Energy No-Load Status Bits ZERO-CROSSING DETECTION ZERO-CROSSING OUTPUT PINS Voltage Channel Zero Crossing Current Channel Zero Crossing ZERO-CROSSING INTERRUPTS ZERO-CROSSING TIMEOUT ZERO-CROSSING THRESHOLD VOLTAGE SAG DETECTION SETTING THE SAGCYC REGISTER SETTING THE SAGLVL REGISTER VOLTAGE SAG INTERRUPT PEAK DETECTION INDICATION OF POWER DIRECTION REVERSE POWER SIGN INDICATION OVERCURRENT AND OVERVOLTAGE DETECTION SETTING THE OVLVL AND OILVL REGISTERS OVERVOLTAGE AND OVERCURRENT INTERRUPTS ALTERNATIVE OUTPUT FUNCTIONS ADE7953 INTERRUPTS PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND CURRENT CHANNEL A) CURRENT CHANNEL B INTERRUPTS COMMUNICATING WITH THE ADE7953 COMMUNICATION AUTODETECTION LOCKING THE COMMUNICATION INTERFACE SPI INTERFACE I2C INTERFACE I2C Write Operations I2C Read Operations UART INTERFACE UART Read UART Write COMMUNICATION VERIFICATION AND SECURITY WRITE PROTECTION COMMUNICATION VERIFICATION CHECKSUM REGISTER ADE7953 REGISTERS ADE7953 REGISTER DESCRIPTIONS Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Current Channel B Registers LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE