Datasheet ADE7854, ADE7858, ADE7868, ADE7878 (Analog Devices) - 88

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ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet Table 39. MASK0 Register (Address 0xE50A) Bit Location Bit Mnemonic Default Value Description
0 AEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active energy registers (AWATTHR, BWATTHR, or CWATTHR) changes. 1 FAEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes. Setting this bit to1 does not have any consequence for ADE7854, ADE7858, and ADE7868. 2 REHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive energy registers (AVARHR, BVARHR, CVARHR) changes. Setting this bit to1 does not have any consequence for ADE7854. 3 FREHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes. Setting this bit to1 does not have any consequence for ADE7854, ADE7858, and ADE7868. 4 VAEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent energy registers (AVAHR, BVAHR, or CVAHR) changes. 5 LENERGY 0 When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of an integration over an integer number of half line cycles set in the LINECYC register. 6 REVAPA 0 When this bit is set to 1, it enables an interrupt when the Phase A active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign. 7 REVAPB 0 When this bit is set to 1, it enables an interrupt when the Phase B active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign. 8 REVAPC 0 When this bit is set to 1, it enables an interrupt when the Phase C active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign. 9 REVPSUM1 0 When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1 datapath changes sign. 10 REVRPA 0 When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting this bit to1 does not have any consequence for ADE7854. 11 REVRPB 0 When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting this bit to1 does not have any consequence for ADE7854. 12 REVRPC 0 When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting this bit to1 does not have any consequence for ADE7854. 13 REVPSUM2 0 When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2 datapath changes sign. 14 CF1 When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the CF1 pin, that is, an active low pulse is generated. The interrupt can be enabled even if the CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 45). 15 CF2 When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2 pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45). 16 CF3 When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45). 17 DREADY 0 When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP computations finish. 18 REVPSUM3 0 When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3 datapath changes sign. 31:19 Reserved 00 0000 0000 Reserved. These bits do not manage any functionality. 0000 Rev. H| Page 88 of 100 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagrams Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Power Management PSM0—Normal Power Mode (All Parts) PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) PSM2—Low Power Mode (ADE7868, ADE7878 Only) PSM3—Sleep Mode (All Parts) Power-Up Procedure Hardcore Reset Software Reset Functionality Theory of Operation Analog Inputs Analog-to-Digital Conversion Antialiasing Filter ADC Transfer Function Current Channel ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt Current Sensor and Digital Integrator Voltage Channel ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling Changing Phase Voltage Datapath POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection SAG Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch—ADE7868, ADE7878 Phase Compensation Reference Circuit Digital Signal Processor Root Mean Square Measurement Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation—ADE7868 and ADE7878 Only Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Active Power Calculation Total Active Power Calculation Fundamental Active Power Calculation—ADE7878 Only Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under A Steady Load Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode Apparent Power Calculation Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Line Cycle Apparent Energy Accumulation Mode Waveform Sampling Mode Energy-to-Frequency Conversion Synchronizing Energy Registers with CFx Outputs CF Outputs for Various Accumulation Modes Sign of Sum-of-Phase Powers in the CFx Datapath No Load Condition No Load Detection Based On Total Active, Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers—ADE7878 Only No Load Detection Based on Apparent Power Checksum Register Interrupts Using the Interrupts with an MCU Serial Interfaces Serial Interface Choice I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Quick Setup as Energy Meter Layout Guidelines Crystal Circuit ADE7878 Evaluation Board Die Version Silicon Anomaly ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Functionality Issues SECTION 1. ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Registers List Outline Dimensions Ordering Guide