Datasheet ADE7763 (Analog Devices) - 8

ManufacturerAnalog Devices
DescriptionSingle-Phase Active and Apparent Energy Metering IC
Pages / Page56 / 8 — ADE7763. Data Sheet. TERMINOLOGY Measurement Error. Phase Error between …
RevisionC
File Format / SizePDF / 841 Kb
Document LanguageEnglish

ADE7763. Data Sheet. TERMINOLOGY Measurement Error. Phase Error between Channels. ADC Offset Error. Gain Error

ADE7763 Data Sheet TERMINOLOGY Measurement Error Phase Error between Channels ADC Offset Error Gain Error

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ADE7763 Data Sheet TERMINOLOGY Measurement Error
when an ac (175 mV rms/120 Hz) signal is introduced to the The error associated with the energy measurement made by the supplies. Any error introduced by this ac signal is expressed ADE7763 is defined by the following formula: as a percentage of the reading—see the Measurement Percent Error = Error definition.  Energy Register ADE7763 −True Energy  For the dc PSR measurement, a reading at nominal supplies     × 100% (5 V) is taken. A second reading is obtained with the same input  True Energy  signal levels when the supplies are varied ±5%. Any error
Phase Error between Channels
introduced is again expressed as a percentage of the reading. The digital integrator and the high-pass filter (HPF) in Channel 1
ADC Offset Error
have a nonideal phase response. To offset this phase response The dc offset associated with the analog inputs to the ADCs. It and equalize the phase response between channels, two phase- means that with the analog inputs connected to AGND, the correction networks are placed in Channel 1: one for the digital ADCs still see a dc analog input signal. The magnitude of the integrator and the other for the HPF. The phase correction offset depends on the gain and input range selection—see the networks correct the phase response of the corresponding Typical Performance Characteristics section. However, when component and ensure a phase match between Channel 1 HPF1 is switched on, the offset is removed from Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range (current) and the power calculation is not affected by this offset. of 45 Hz to 65 Hz with the digital integrator off. With the digital The offsets can be removed by performing an offset calibration— integrator on, the phase is corrected to within ±0.4° over a see the Analog Inputs section. range of 45 Hz to 65 Hz.
Gain Error Power Supply Rejection
The difference between the measured ADC output code (minus This quantifies the ADE7763 measurement error as a percentage the offset) and the ideal output code—see the Channel 1 ADC of the reading when the power supplies are varied. For the ac and Channel 2 ADC sections. It is measured for each of the PSR measurement, a reading at nominal supplies (5 V) is taken. input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The A second reading is obtained with the same input signal levels difference is expressed as a percentage of the ideal code. Rev. C | Page 8 of 56 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Terminology Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs di/dt Current Sensor and Digital Integrator Zero-Crossing Detection Zero-Crossing Timeout Period Measurement Power Supply Monitor Line Voltage Sag Detection Sag Level Set Peak Detection Peak Level Set Peak Level Record Interrupts Using Interrupts with an MCU Interrupt Timing Temperature Measurement Analog-to-Digital Conversion Antialias Filter ADC Transfer Function Reference Circuit Channel 1 ADC Channel 1 Sampling Channel 1 RMS Calculation Channel 1 RMS Offset Compensation Channel 2 ADC Channel 2 Sampling Channel 2 RMS Calculation Channel 2 RMS Offset Compensation Phase Compensation Active Power Calculation Energy Calculation Integration Time under Steady Load Power Offset Calibration Energy-to-Frequency Conversion Line Cycle Energy Accumulation Mode Positive-Only Accumulation Mode No-Load Threshold Apparent Power Calculation Apparent Power Offset Calibration Apparent Energy Calculation Integration Times under Steady Load Line Apparent Energy Accumulation Energies Scaling Calibrating an Energy Meter Watt Gain Calibrating Watt Gain Using a Reference Meter Example Calibrating Watt Gain Using an Accurate Source Example Watt Offset Calibrating Watt Offset Using a Reference Meter Example Calibrating Watt Offset with an Accurate Source Example Phase Calibration Calibrating Phase Using a Reference Meter Example Calibrating Phase with an Accurate Source Example VRMS and IRMS Calibration Apparent Energy CLKIN Frequency Suspending Functionality Checksum Register Serial Interface ADE7763 Serial Write Operation Serial Read Operation Registers Register Descriptions Communication Register Mode Register (0x09) Outline Dimensions Ordering Guide CH1OS Register (0x0D) Outline Dimensions Ordering Guide
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