Datasheet ADE7758 (Analog Devices) - 10

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ADE7758 Data Sheet Pin No. Mnemonic Description
17 VARCF Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers (see the Reactive Power Frequency Output section). 18 IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: an active energy register at half level, an apparent energy register at half level, and waveform sampling up to 26 kSPS (see the Interrupts section). 19 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements 20 CLKOUT A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. 21 CS Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial bus with several other devices (see the Serial Interface section). 22 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the Serial Interface section). 23 SCLK Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock (see the Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator outputs. 24 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus (see the Serial Interface section). Rev. E | Page 10 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ANTIALIASING FILTER ANALOG INPUTS CURRENT CHANNEL ADC Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR PEAK CURRENT DETECTION Peak Current Detection Using the PEAK Register OVERCURRENT DETECTION INTERRUPT VOLTAGE CHANNEL ADC Voltage Channel Sampling ZERO-CROSSING DETECTION Zero-Crossing Timeout PHASE COMPENSATION PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG LEVEL SET PEAK VOLTAGE DETECTION Peak Voltage Detection Using the VPEAK Register Overvoltage Detection Interrupt PHASE SEQUENCE DETECTION POWER-SUPPLY MONITOR REFERENCE CIRCUIT TEMPERATURE MEASUREMENT ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS Gain Adjust ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation No-Load Threshold Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Active Power Frequency Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Reactive Power Frequency Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Apparent Power Frequency Output Line Cycle Apparent Energy Accumulation Mode ENERGY REGISTERS SCALING WAVEFORM SAMPLING MODE CALIBRATION Calibration Using Pulse Output Gain Calibration Using Pulse Output Example: Watt Gain Calibration of Phase A Using Pulse Output Phase Calibration Using Pulse Output Example: Phase Calibration of Phase A Using Pulse Output Power Offset Calibration Using Pulse Output Example: Offset Calibration of Phase A Using Pulse Output Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Example: Watt Gain Calibration Using Line Accumulation Phase Calibration Using Line Accumulation Example: Phase Calibration Using Line Accumulation Power Offset Calibration Using Line Accumulation Example: Power Offset Calibration Using Line Accumulation Calibration of IRMS and VRMS Offset Example: Calibration of RMS Offsets CHECKSUM REGISTER INTERRUPTS USING THE INTERRUPTS WITH AN MCU INTERRUPT TIMING SERIAL INTERFACE SERIAL WRITE OPERATION SERIAL READ OPERATION ACCESSING THE ON-CHIP REGISTERS REGISTERS COMMUNICATIONS REGISTER OPERATIONAL MODE REGISTER (0x13) MEASUREMENT MODE REGISTER (0x14) WAVEFORM MODE REGISTER (0x15) COMPUTATIONAL MODE REGISTER (0x16) LINE CYCLE ACCUMULATION MODE REGISTER (0x17) INTERRUPT MASK REGISTER (0x18) INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) OUTLINE DIMENSIONS ORDERING GUIDE