Datasheet ADE7754 (Analog Devices) - 25

ADE7754
and voltage gain registers. See the Current RMS Calculation The total apparent power calculated by the ADE7754 depends on and Voltage RMS Calculation sections. Only the effect of the the configuration of the VAMOD bits in the VAMode register. apparent power gain is shown on Figure 35. The minimum Each term of the formula used can be disabled or enabled by the output range is given when the apparent power gain register setting VASEL bits, respectively, to Logic 0 or Logic 1 in the content is equal to 800h and the maximum range is given by VAMode register. The different configurations are described in writing 7FFh to the apparent power gain register. This can be Table IV. used to calibrate the apparent power (or energy) calculation in the ADE7754 for each phase and the total apparent energy.
Table IV. Total Apparent Power Calculation
See the Total Apparent Power Calculation section.
VAMOD VASEL0 VASEL1 VASEL2 APPARENT POWER VOLTAGE CHANNEL AND
0d V × I × I × I
CURRENT CHANNEL 0.5V/GAIN
ARMS ARMS + VBRMS BRMS + VCRMS CRMS
13A929h + 150% FS
1d V × ARMS IARMS +(VARMS + VCRMS)
D1B71h + 100% FS
/2 I × BRMS + VCRMS ICRMS
68DB9h + 50% FS 00000h AVAGAIN[11:0]
2d V × × × ARMS IARMS + VARMS IBRMS + VCRMS ICRMS
F97247h – 50% FS F2E48Fh – 100% FS
Note that VARMS, VBRMS, VCRMS, IARMS, IBRMS, and ICRMS represent
EC56D7h – 150% FS 000h 7FFh 800h
the voltage and current channels RMS values of the corresponding registers. Figure 35. Apparent Power Calculation Output Range For example, for VAMOD = 1, the formula used to process the
Apparent Power Offset Calibration
apparent power is Each rms measurement includes an offset compensation register   to calibrate and eliminate the dc component in the rms value. AVAG Total Apparent Power =V × I × 1+ ARMS ARMS See the Current RMS Calculation and Voltage RMS Calculation  212  sections. The voltage and current rms values are then multiplied V ( V )  BVAG  in the apparent power signal processing. Because no additional ARMS CRMS + + × I × 1+ BRMS 2  212  offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal  CVAG  processing. The offset compensation of the apparent power V + × I × 1+ CRMS CRMS  212  measurement in each phase is done by calibrating each indi- vidual rms measurement. The polyphase meter configuration determines which formula should be used to calculate the apparent energy. The American
TOTAL APPARENT POWER CALCULATION
ANSI C12.10 standard defines the different configurations of The sum of the apparent powers coming from each phase gives the meter. Table V describes which mode should be chosen for the total apparent power consumption. Different combinations different configurations. of the three phases can be selected in the sum by setting Bits 7 and 6 of the VAMode register (mnemonic VAMOD[1:0]). Figure 36
Table V. Meter Form Configuration
demonstrates the calculation of the total apparent power.
PHASE A ANSI Meter Form VAMOD VASEL I
5S/13S 3-wire Delta 0 3 or 5 or 6
A RMS 24
6S/14S 4-wire Wye 1 7
AAPGAIN VARMS
8S/15S 4-wire Delta 2 7
VA RMS AVAGAIN
9S/16S 4-wire Wye 0 7
AVGAIN
Different gain calibration parameters are offered in the ADE7754
PHASE B
to cover the calibration of the meter in different configurations.
I
The APGAIN, VGAIN, and VAGAIN registers have different
B RMS TOTAL APPARENT 24 POWER SIGNAL
purposes in the signal processing of the ADE7754. APGAIN
BAPGAIN
registers affect the apparent power calculation but should be
VB RMS BVAGAIN
used only for active power calibration. VAGAIN registers are
BVGAIN
used to calibrate the apparent power calculation. VGAIN regis- ters have the same effect as VAGAIN registers when VAMOD =
VARMS % + +
0 or 2. They should be left at their default value in these modes.
V 2
VGAIN registers should be used to compensate gain mismatches
CRMS PHASE C
between channels in VAMOD = 1.
I
As mentioned previously, the offset compensation of the phase
C RMS 24
apparent power calculation is done in each individual rms mea-
CAPGAIN VCRMS
surement signal processing. See the Apparent Power Offset
VC RMS CVAGAIN
Calibration section.
CVGAIN
Figure 36. Total Apparent Power Calculation REV. 0 –25– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics TERMINOLOGY Measurement Error Phase Error Between Channels Power Supply Rejection ADC Offset Error Gain Error Gain Error Match POWER SUPPLY MONITOR ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialias Filter CURRENT CHANNEL ADC Current Channel ADC Gain Adjust Current Channel Sampling VOLTAGE CHANNEL ADC ZERO-CROSSING DETECTION Zero-Crossing Timeout PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG Level Set PEAK DETECTION Peak Level Set TEMPERATURE MEASUREMENT PHASE COMPENSATION ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Gain Adjust Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Gain Adjust Voltage RMS Offset Compensation ACTIVE POWER CALCULATION Power Offset Calibration Reverse Power Information TOTAL ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Times Under Steady Load Energy to Frequency Conversion No Load Threshold Mode Selection of the Sum of the Three Active Energies LINE ENERGY ACCUMULATION REACTIVE POWER CALCULATION TOTAL REACTIVE POWER CALCULATION Reactive Energy Accumulation Selection APPARENT POWER CALCULATION Apparent Power Offset Calibration TOTAL APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Integration Times under Steady Load LINE APPARENT ENERGY ACCUMULATION ENERGIES SCALING CHECK SUM REGISTER SERIAL INTERFACE Serial Write Operation Serial Read Operation INTERRUPTS Using Interrupts with an MCU Interrupt Timing ACCESSING THE ADE7754 ON-CHIP REGISTERS Communications Register Operational Mode Register (0Ah) Gain Register (18h) CFNUM Register (25h) Measurement Mode Register (0Bh) Waveform Mode Register (0Ch) Watt Mode Register (0Dh) VA Mode Register (0Eh) Interrupt Enable Register (0Fh) Interrupt Status Register (10h)/Reset Interrupt Status Register (11h) OUTLINE DIMENSIONS