Datasheet LT8606, LT8606B (Analog Devices) - 9

LT8606/LT8606B
PIN FUNCTIONS BST:
This pin is used to provide a drive voltage, higher
FB:
The LT8606 regulates the FB pin to 0.778V. Connect than the input voltage, to the topside power switch. Place the feedback resistor divider tap to this pin. a 0.1µF boost capacitor as close as possible to the IC. Do
TR/SS (MSOP Only):
Output Tracking and Soft-Start Pin. not place a resistor in series with this pin. This pin allows user control of output voltage ramp rate
SW:
The SW pin is the output of the internal power during start-up. A TR/SS voltage below 0.778V forces the switches. Connect this pin to the inductor and boost LT8606 to regulate the FB pin to equal the TR/SS pin volt- capacitor. This node should be kept small on the PCB for age. When TR/SS is above 0.778V, the tracking function good performance. is disabled and the internal reference resumes control of
INTV
the error amplifier. An internal 2μA pull-up current from
CC
Internal 3.5V Regulator Bypass Pin. The internal power drivers and control circuits are powered from this INTVCC on this pin allows a capacitor to program out- voltage. INTV put voltage slew rate. This pin is pulled to ground with a CC max output current is 20mA. Voltage on INTV 300Ω MOSFET during shutdown and fault conditions; use CC will vary between 2.8V and 3.5V. Decouple this pin to power ground with at least a 1μF low ESR a series resistor if driving from a low impedance output. ceramic capacitor. Do not load the INTV There is no TR/SS pin on the LT8606 or LT8606B DFN CC pin with exter- nal circuitry. and the node is internally floated.
RT:
A resistor is tied between RT and ground to set the
PG:
The PG pin is the open-drain output of an internal switching frequency. When synchronizing, the R comparator. PG remains low until the FB pin is within T resistor should be chosen to set the LT8606 switching frequency ±8.5% of the final regulation voltage, and there are no to equal or below the lowest synchronization input. fault conditions. PG is valid when VIN is above 3.2V and when EN/UV is high. PG is pulled low when VIN is above
SYNC (MSOP Only):
External Clock Synchronization 3.2V and EN/UV is low. If VIN is near zero, PG will be high Input. Ground this pin for low ripple Burst Mode operation impedance. at low output loads. Tie to a clock source for synchroni- zation to an external frequency. Leave floating for pulse-
VIN:
The VIN pin supplies current to the LT8606 internal skipping mode with no spread spectrum modulation. Tie circuitry and to the internal topside power switch. This pin to INTV must be locally bypassed. Be sure to place the positive CC or tie to a voltage between 3.2V and 5.0V for pulse-skipping mode with spread spectrum modulation. terminal of the input capacitor as close as possible to the When in pulse-skipping mode, the I VIN pins, and the negative capacitor terminal as close as Q regulating no load will increase to several mA. There is no SYNC pin on the possible to the GND pins. LT8606 DFN package. The LT8606 DFN package internally
EN/UV:
The LT8606 is shut down when this pin is low and ties SYNC to ground. The LT8606B package internal y active when this pin is high. The hysteretic threshold volt- floats SYNC. age is 1.05V going up and 1.00V going down. Tie to VIN if the shutdown feature is not used. An external resistor divider from VIN can be used to program a VIN threshold below which the LT8606 will shut down.
GND:
Exposed Pad Pin. The exposed pad must be con- nected to the negative terminal of the input capacitor and soldered to the PCB in order to lower the thermal resistance. Rev C For more information www.analog.com 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS