Datasheet LTC3895 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 150V Low IQ, Synchronous Step-Down DC/DC Controller |
| Pages / Page | 38 / 5 — elecTrical characTerisTics. The. denotes the specifications which apply … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
elecTrical characTerisTics. The. denotes the specifications which apply over the specified operating
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LTC3895
elecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC LDO Regulator
VINTVCC INTVCC Voltage ICC = 0mA to 2mA 4.7 5.0 5.2 V
Oscillator and Phase-Locked Loop
Programmable Frequency RFREQ = 25k, PLLIN = DC Voltage 105 kHz Programmable Frequency RFREQ = 65k, PLLIN = DC Voltage 375 440 505 kHz Programmable Frequency RFREQ =105k, PLLIN = DC Voltage 835 kHz Low Fixed Frequency VFREQ = 0V, PLLIN = DC Voltage 320 350 380 kHz High Fixed Frequency VFREQ = INTVCC, PLLIN = DC Voltage 485 535 585 kHz fSYNC Synchronizable Frequency PLLIN = External Clock l 75 850 kHz PLLIN Input High Level PLLIN = External Clock l 2.8 V PLLIN Input Low Level PLLIN = External Clock l 0.5 V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.02 0.04 V IPGOOD PGOOD Leakage Current VPGOOD = 3.3V 10 µA PGOOD Trip Level VFB with Respect to Set Regulated Voltage VFB Ramping Negative –13 –10 –7 % Hysteresis 2.5 % VFB with Respect to Set Regulated Voltage VFB Ramping Positive 7 10 13 % Hysteresis 2.5 % Delay for Reporting a Fault 40 µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
The LTC3895 is tested in a feedback loop that servos VITH to a may cause permanent damage to the device. Exposure to any Absolute specified voltage and measures the resultant VFB. The specification at 85°C Maximum Ratings for extended periods may affect device reliability and is not tested in production and is assured by design, characterization and lifetime. correlation to production testing at other temperatures (125°C for the
Note 2:
The LTC3895 is tested under pulsed load conditions such that T LTC3895E and LTC3895I, 150°C for the LTC3895H). For the LTC3895I J ≈ T and LTC3895H, the specification at 0°C is not tested in production and is A. The LTC3895E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction assured by design, characterization and correlation to production testing temperature range are assured by design, characterization and correlation at –40°C. with statistical process controls. The LTC3895I is guaranteed over the
Note 5:
Dynamic supply current is higher due to the gate charge being –40°C to 125°C operating junction temperature range and the LTC3895H delivered at the switching frequency. See the Applications information is guaranteed over the –40°C to 150°C operating junction temperature section. range. Note that the maximum ambient temperature consistent with
Note 6:
Rise and fall times are measured using 10% and 90% levels. Delay these specifications is determined by specific operating conditions in times are measured using 50% levels. conjunction with board layout, the rated package thermal impedance
Note 7:
The minimum on-time condition is specified for an inductor and other environmental factors. High temperatures degrade operating peak-to-peak ripple current >40% of I lifetimes; operating lifetime is derated for junction temperatures greater MAX (See Minimum On-Time Considerations in the Applications Information section). than 125ºC. The junction temperature (TJ, in °C) is calculated from the ambient temperature (T
Note 8:
Do not apply a voltage or current source to these pins. They must A, in °C) and power dissipation (PD, in Watts) according to the formula: be connected to capacitive loads only, otherwise permanent damage may occur. TJ = TA + (PD • θJA)
Note 9:
Do not apply a voltage or current source to the NDRV pin, other where θJA = 28°C/W for the TSSOP package. than tying NDRV to DRVCC when not used. If used it must be connected
Note 3:
This IC includes overtemperature protection that is intended to to capacitive loads only (see DRVCC Regulators in the Applications protect the device during momentary overload conditions. The maximum Information section), otherwise permanent damage may occur. rated junction temperature will be exceeded when this protection is active.
Note 10:
The minimum input supply operating range is dependent on the Continuous operation above the specified absolute maximum operating DRV junction temperature may impair device reliability or permanently damage CC UVLO thresholds as determined by the DRVUV pin setting. the device. 3895fa For more information www.linear.com/LTC3895 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
elecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V, VPRG = FLOAT unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC LDO Regulator
VINTVCC INTVCC Voltage ICC = 0mA to 2mA 4.7 5.0 5.2 V
Oscillator and Phase-Locked Loop
Programmable Frequency RFREQ = 25k, PLLIN = DC Voltage 105 kHz Programmable Frequency RFREQ = 65k, PLLIN = DC Voltage 375 440 505 kHz Programmable Frequency RFREQ =105k, PLLIN = DC Voltage 835 kHz Low Fixed Frequency VFREQ = 0V, PLLIN = DC Voltage 320 350 380 kHz High Fixed Frequency VFREQ = INTVCC, PLLIN = DC Voltage 485 535 585 kHz fSYNC Synchronizable Frequency PLLIN = External Clock l 75 850 kHz PLLIN Input High Level PLLIN = External Clock l 2.8 V PLLIN Input Low Level PLLIN = External Clock l 0.5 V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.02 0.04 V IPGOOD PGOOD Leakage Current VPGOOD = 3.3V 10 µA PGOOD Trip Level VFB with Respect to Set Regulated Voltage VFB Ramping Negative –13 –10 –7 % Hysteresis 2.5 % VFB with Respect to Set Regulated Voltage VFB Ramping Positive 7 10 13 % Hysteresis 2.5 % Delay for Reporting a Fault 40 µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
The LTC3895 is tested in a feedback loop that servos VITH to a may cause permanent damage to the device. Exposure to any Absolute specified voltage and measures the resultant VFB. The specification at 85°C Maximum Ratings for extended periods may affect device reliability and is not tested in production and is assured by design, characterization and lifetime. correlation to production testing at other temperatures (125°C for the
Note 2:
The LTC3895 is tested under pulsed load conditions such that T LTC3895E and LTC3895I, 150°C for the LTC3895H). For the LTC3895I J ≈ T and LTC3895H, the specification at 0°C is not tested in production and is A. The LTC3895E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction assured by design, characterization and correlation to production testing temperature range are assured by design, characterization and correlation at –40°C. with statistical process controls. The LTC3895I is guaranteed over the
Note 5:
Dynamic supply current is higher due to the gate charge being –40°C to 125°C operating junction temperature range and the LTC3895H delivered at the switching frequency. See the Applications information is guaranteed over the –40°C to 150°C operating junction temperature section. range. Note that the maximum ambient temperature consistent with
Note 6:
Rise and fall times are measured using 10% and 90% levels. Delay these specifications is determined by specific operating conditions in times are measured using 50% levels. conjunction with board layout, the rated package thermal impedance
Note 7:
The minimum on-time condition is specified for an inductor and other environmental factors. High temperatures degrade operating peak-to-peak ripple current >40% of I lifetimes; operating lifetime is derated for junction temperatures greater MAX (See Minimum On-Time Considerations in the Applications Information section). than 125ºC. The junction temperature (TJ, in °C) is calculated from the ambient temperature (T
Note 8:
Do not apply a voltage or current source to these pins. They must A, in °C) and power dissipation (PD, in Watts) according to the formula: be connected to capacitive loads only, otherwise permanent damage may occur. TJ = TA + (PD • θJA)
Note 9:
Do not apply a voltage or current source to the NDRV pin, other where θJA = 28°C/W for the TSSOP package. than tying NDRV to DRVCC when not used. If used it must be connected
Note 3:
This IC includes overtemperature protection that is intended to to capacitive loads only (see DRVCC Regulators in the Applications protect the device during momentary overload conditions. The maximum Information section), otherwise permanent damage may occur. rated junction temperature will be exceeded when this protection is active.
Note 10:
The minimum input supply operating range is dependent on the Continuous operation above the specified absolute maximum operating DRV junction temperature may impair device reliability or permanently damage CC UVLO thresholds as determined by the DRVUV pin setting. the device. 3895fa For more information www.linear.com/LTC3895 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
