Datasheet LT3992 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Monolithic Dual Tracking 3A Step-Down Switching Regulator |
| Pages / Page | 36 / 10 — block DiagraM. CHANNEL 1. Figure 1. LT3992 Block Diagram |
| File Format / Size | PDF / 678 Kb |
| Document Language | English |
block DiagraM. CHANNEL 1. Figure 1. LT3992 Block Diagram
Model Line for this Datasheet
Text Version of Document
LT3992
block DiagraM
VIN1 V 1.32V + IN1 SHDN1 –
CHANNEL 1
BST1 THERMAL DROPOUT SHUTDOWN ENHANCEMENT PRE S DRIVER – Q SW1 CIRCUITRY 2.5V + R D1 12µA PRE IND1 SS1 – S Q + + R – 110mV VOUT1 VC1 R1 FB1 2.5V CMPI1 R2 12µA ILIM1 + CMPO1 + 0.806V 0.72V + – RLIM SLOPE 2.5V COMPENSATION – 12µA RT/SYNC TJ INTERNAL R3 2.5V CLK1 2.5V VIN1 + REGULATOR OSCILLATOR MASTER CLOCK 2.9V – AND CLKOUT 12µA AND AGC REFERENCES DIV CLK2 TO CHANNEL 2 GND RDIV 3992 F01
Figure 1. LT3992 Block Diagram
The LT3992 is a dual channel, constant frequency, current is then divided by 1, 2, 4 or 8 depending on the voltage mode buck converter with internal 4.6A switches. Each present at the DIV pin. Channel 2’s clock runs at the master channel can be independently controlled with the exception clock frequency with a 180° phase shift from channel 1. that VIN1 must be above the typically 2.9V undervoltage Alternatively, if a synchronization signal is detected by lockout threshold to power the common internal regulator, the LT3992 the RT/SYNC pin, the master clock will be oscillator and thermometer circuitry. generated at the incoming frequency on the rising edge If the SHDN1 pin is taken below its 1.32V threshold the of the synchronization pulse with channel 1 in phase with LT3992 will be placed in a low quiescent current mode. In this the synchronization signal. Frequency division and phase mode the LT3992 typically draws 6µA from VIN1 and <1µA remains the same as the internally generated master clock. from VIN2. When the SHDN pin is driven above 1.32V, the In addition, the internal slope compensation will be au- internal bias circuits turn on generating an internal regulated tomatically adjusted to prevent subharmonic oscillation voltage, 0.806VFB, 12µA RT/SYNC, DIV and ILIM current during synchronization. In either mode of oscillator op- references, and a POR signal which sets the soft-start latch. eration, a square wave with the master clock frequency, Once the internal reference reaches its regulation point, synchronized to channel 1 is present at the CLKOUT pin. the internal oscillator will start generating a master clock The two regulators are constant frequency, current mode signal for the two regulators at a frequency determined by step-down converters. Current mode regulators are con- the voltage present at the RT/SYNC pin. The channel 1 clock trolled by an internal clock and two feedback loops that 3992fa 10 For more information www.linear.com/LT3992 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
block DiagraM
VIN1 V 1.32V + IN1 SHDN1 –
CHANNEL 1
BST1 THERMAL DROPOUT SHUTDOWN ENHANCEMENT PRE S DRIVER – Q SW1 CIRCUITRY 2.5V + R D1 12µA PRE IND1 SS1 – S Q + + R – 110mV VOUT1 VC1 R1 FB1 2.5V CMPI1 R2 12µA ILIM1 + CMPO1 + 0.806V 0.72V + – RLIM SLOPE 2.5V COMPENSATION – 12µA RT/SYNC TJ INTERNAL R3 2.5V CLK1 2.5V VIN1 + REGULATOR OSCILLATOR MASTER CLOCK 2.9V – AND CLKOUT 12µA AND AGC REFERENCES DIV CLK2 TO CHANNEL 2 GND RDIV 3992 F01
Figure 1. LT3992 Block Diagram
The LT3992 is a dual channel, constant frequency, current is then divided by 1, 2, 4 or 8 depending on the voltage mode buck converter with internal 4.6A switches. Each present at the DIV pin. Channel 2’s clock runs at the master channel can be independently controlled with the exception clock frequency with a 180° phase shift from channel 1. that VIN1 must be above the typically 2.9V undervoltage Alternatively, if a synchronization signal is detected by lockout threshold to power the common internal regulator, the LT3992 the RT/SYNC pin, the master clock will be oscillator and thermometer circuitry. generated at the incoming frequency on the rising edge If the SHDN1 pin is taken below its 1.32V threshold the of the synchronization pulse with channel 1 in phase with LT3992 will be placed in a low quiescent current mode. In this the synchronization signal. Frequency division and phase mode the LT3992 typically draws 6µA from VIN1 and <1µA remains the same as the internally generated master clock. from VIN2. When the SHDN pin is driven above 1.32V, the In addition, the internal slope compensation will be au- internal bias circuits turn on generating an internal regulated tomatically adjusted to prevent subharmonic oscillation voltage, 0.806VFB, 12µA RT/SYNC, DIV and ILIM current during synchronization. In either mode of oscillator op- references, and a POR signal which sets the soft-start latch. eration, a square wave with the master clock frequency, Once the internal reference reaches its regulation point, synchronized to channel 1 is present at the CLKOUT pin. the internal oscillator will start generating a master clock The two regulators are constant frequency, current mode signal for the two regulators at a frequency determined by step-down converters. Current mode regulators are con- the voltage present at the RT/SYNC pin. The channel 1 clock trolled by an internal clock and two feedback loops that 3992fa 10 For more information www.linear.com/LT3992 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
