Datasheet LT3845A (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | High Voltage Synchronous Current Mode Step-Down Controller with Adjustable Operating Frequency |
| Pages / Page | 26 / 7 — PIN FUNCTIONS BG:. PGND:. BOOST:. SENSE–:. SENSE+:. BURST_EN:. SGND:. … |
| File Format / Size | PDF / 295 Kb |
| Document Language | English |
PIN FUNCTIONS BG:. PGND:. BOOST:. SENSE–:. SENSE+:. BURST_EN:. SGND:. SHDN:. CSS:. SW:. SYNC:. SET:
Model Line for this Datasheet
Text Version of Document
LT3845A
PIN FUNCTIONS BG:
The BG pin is the gate drive for the bottom N-channel
PGND:
The PGND pin is the high-current ground reference MOSFET. Since very fast high currents are driven from for internal low side switch driver and the VCC regulator this pin, connect it to the gate of the power MOSFET circuit. Connect the pin directly to the negative terminal with a short and wide, typically 0.02" width, PCB trace to of the VCC decoupling capacitor. See the Application minimize inductance. Information section for helpful hints on PCB layout of
BOOST:
The BOOST pin is the supply for the bootstrapped grounds. gate drive and is externally connected to a low ESR ceramic
SENSE–:
The SENSE– pin is the negative input for the boost capacitor referenced to SW pin. The recommended current sense amplifier and is connected to the VOUT side value of the BOOST capacitor, CBOOST, is at least 50 times of the sense resistor for step-down applications. greater than the total gate capacitance of the topside MOSFET.
SENSE+:
The SENSE+ pin is the positive input for the current In most applications 0.1µF is adequate. The maximum voltage sense amplifier and is connected to the inductor side of that this pin sees is VIN + VCC, ground referred. the sense resistor for step-down applications.
BURST_EN:
Burst Mode Operation Enable Pin. This pin also
SGND:
The SGND pin is the low noise ground reference. controls reverse-current inhibit mode of operation. When It should be connected to the –V the pin voltage is below 0.5V, Burst Mode operation and OUT side of the output capacitors. Careful layout of the PCB is necessary to keep reverse-current inhibit functions are enabled. When the pin high currents away from this SGND connection. See the voltage is above 0.5V, Burst Mode operation is disabled, Application Information section for helpful hints on PCB but reverse-current inhibit operation is maintained. In layout of grounds. this mode of operation (BURST_EN = VFB) there is a 1mA minimum load requirement. Reverse-current inhibit is
SHDN:
The SHDN pin has a precision IC enable threshold disabled when the pin voltage is above 2.5V. This pin is of 1.35V (rising) with 120mV of hysteresis. It is used to typically shorted to ground to enable Burst Mode operation implement an undervoltage lockout (UVLO) circuit. See and reverse-current inhibit, shorted to V Application Information section for implementing a UVLO FB to disable Burst Mode operation while enabling reverse-current inhibit, function. When the SHDN pin is pulled below a transistor and connected to V VBE (0.7V), a low current shutdown mode is entered, all CC pin to disable both functions. See Applications Information section. internal circuitry is disabled and the VIN supply current is reduced to approximately 9µA. Typical pin input bias
CSS:
The soft-start pin is used to program the supply soft- current is <10nA and the pin is internally clamped to 6V. start function. Use the following formula to calculate CSS If the function is not used, this pin may be tied to VIN for a given output voltage slew rate: through a high value resistor. CSS = 2µA(tSS/1.231V)
SW:
Reference for VBOOST Supply and High Current Return The pin should be left unconnected when not using the for Bootstrapped Switch. soft-start function.
SYNC:
The Sync pin provides an external clock input for
f
synchronization of the internal oscillator. R
SET:
The fSET pin programs the oscillator frequency with an SET is set such external resistor, R that the internal oscillator frequency is 10% to 25% below SET. The resistor is required even when supplying external sync clock signal. See the Applications the external clock frequency. If unused the Sync pin is Information section for resistor value selection details. connected to SGND. For more information see “Oscillator Sync” in the Application Information section of this data sheet. Sync pin not available in PDIP package. 3845afa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS BG:
The BG pin is the gate drive for the bottom N-channel
PGND:
The PGND pin is the high-current ground reference MOSFET. Since very fast high currents are driven from for internal low side switch driver and the VCC regulator this pin, connect it to the gate of the power MOSFET circuit. Connect the pin directly to the negative terminal with a short and wide, typically 0.02" width, PCB trace to of the VCC decoupling capacitor. See the Application minimize inductance. Information section for helpful hints on PCB layout of
BOOST:
The BOOST pin is the supply for the bootstrapped grounds. gate drive and is externally connected to a low ESR ceramic
SENSE–:
The SENSE– pin is the negative input for the boost capacitor referenced to SW pin. The recommended current sense amplifier and is connected to the VOUT side value of the BOOST capacitor, CBOOST, is at least 50 times of the sense resistor for step-down applications. greater than the total gate capacitance of the topside MOSFET.
SENSE+:
The SENSE+ pin is the positive input for the current In most applications 0.1µF is adequate. The maximum voltage sense amplifier and is connected to the inductor side of that this pin sees is VIN + VCC, ground referred. the sense resistor for step-down applications.
BURST_EN:
Burst Mode Operation Enable Pin. This pin also
SGND:
The SGND pin is the low noise ground reference. controls reverse-current inhibit mode of operation. When It should be connected to the –V the pin voltage is below 0.5V, Burst Mode operation and OUT side of the output capacitors. Careful layout of the PCB is necessary to keep reverse-current inhibit functions are enabled. When the pin high currents away from this SGND connection. See the voltage is above 0.5V, Burst Mode operation is disabled, Application Information section for helpful hints on PCB but reverse-current inhibit operation is maintained. In layout of grounds. this mode of operation (BURST_EN = VFB) there is a 1mA minimum load requirement. Reverse-current inhibit is
SHDN:
The SHDN pin has a precision IC enable threshold disabled when the pin voltage is above 2.5V. This pin is of 1.35V (rising) with 120mV of hysteresis. It is used to typically shorted to ground to enable Burst Mode operation implement an undervoltage lockout (UVLO) circuit. See and reverse-current inhibit, shorted to V Application Information section for implementing a UVLO FB to disable Burst Mode operation while enabling reverse-current inhibit, function. When the SHDN pin is pulled below a transistor and connected to V VBE (0.7V), a low current shutdown mode is entered, all CC pin to disable both functions. See Applications Information section. internal circuitry is disabled and the VIN supply current is reduced to approximately 9µA. Typical pin input bias
CSS:
The soft-start pin is used to program the supply soft- current is <10nA and the pin is internally clamped to 6V. start function. Use the following formula to calculate CSS If the function is not used, this pin may be tied to VIN for a given output voltage slew rate: through a high value resistor. CSS = 2µA(tSS/1.231V)
SW:
Reference for VBOOST Supply and High Current Return The pin should be left unconnected when not using the for Bootstrapped Switch. soft-start function.
SYNC:
The Sync pin provides an external clock input for
f
synchronization of the internal oscillator. R
SET:
The fSET pin programs the oscillator frequency with an SET is set such external resistor, R that the internal oscillator frequency is 10% to 25% below SET. The resistor is required even when supplying external sync clock signal. See the Applications the external clock frequency. If unused the Sync pin is Information section for resistor value selection details. connected to SGND. For more information see “Oscillator Sync” in the Application Information section of this data sheet. Sync pin not available in PDIP package. 3845afa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
