Datasheet LTC6915 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Zero Drift, Precision Instrumentation Amplifier with Digitally Programmable Gain |
| Pages / Page | 18 / 10 — pin FuncTions (DFN/GN). IN – (Pin 1/Pin 2):. SHDN (Pin 1 GN Package … |
| File Format / Size | PDF / 297 Kb |
| Document Language | English |
pin FuncTions (DFN/GN). IN – (Pin 1/Pin 2):. SHDN (Pin 1 GN Package Only):. IN+ (Pin 2/Pin 3):. DGND (Pin 8/Pin 10):
Model Line for this Datasheet
Text Version of Document
LTC6915
pin FuncTions (DFN/GN) IN – (Pin 1/Pin 2):
Inverting Analog Input. gain control code. In parallel mode operation, if the data
SHDN (Pin 1 GN Package Only):
Shutdown Pin. The IC is in to DOUT (Pin 9) is from a voltage source greater than V+ shut down when SHDN is tied to V+. An internal current (Pin 12), then connect a resistor between the voltage source source pulls this pin to V– when floating. and DOUT to limit the current into Pin 9 to 5mA or less.
IN+ (Pin 2/Pin 3):
Noninverting Analog Input.
DGND (Pin 8/Pin 10):
Digital Ground.
V– (Pin 3/Pin 4):
Negative Supply.
PARALLEL_SERIAL (Pin 9/Pin 11):
Interface Selection Input. When tied to V+, the interface is in parallel mode,
CS(D0) (Pin 4/Pin 6):
TTL Level Input. When in serial i.e., the PGA gain is defined by the parallel codes (D3 ~ control mode, this pin is the chip select input (active low); D0), i.e., CS(D0), DATA(D1), CLK(D2), and DOUT(D3). in parallel control mode, this pin is the LSB of the parallel When PARALLEL_SERIAL pin is tied to V–, the PGA gain gain control code. is set by the serial interface.
DIN(D1) (Pin 5/Pin 7):
TTL Level Input. When in serial
REF (Pin 10/Pin 13):
Voltage Reference for PGA output. control mode, this pin is the serial input data; in paral- lel mode, this pin is the second LSB of the parallel gain
OUT (Pin 11/Pin 15):
Amplifier Output. The typical current control code. sourcing/sinking of the OUT pin is 1mA. For minimum gain error, the load resistance should be 1k or greater
HOLD_THRU (Pin 5 GN Package Only):
TTL Level Input (refer to the Output Voltage Swing vs Output Current and for Parallel Control Mode. When HOLD_THRU is high, the Gain Error vs Load Resistance in the Typical Performance parallel data is latched in an internal D-latch. Characteristics section).
CLK(D2) (Pin 6/Pin 8):
TTL Level Input. When in serial
V+ (Pin 12/Pin 16):
Positive Supply. control mode, this pin is the clock of the serial interface; in parallel mode, this pin is the third LSB of the parallel
SENSE (Pin 14 GN Package Only):
Sense Pin. When the gain control code. PGA drives a low resistance load and the interconnect resistance between the OUT pin and the load is not neg-
DOUT(D3) (Pin 7/Pin 9):
TTL Level Input. When in serial ligible, tying the SENSE pin as close as possible to the control mode, this pin is the output of the serial data; in load can improve the gain accuracy. parallel mode, this pin is the MSB of the 4-bit parallel 6915fb 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Operation Typical Application Package Description Revision History Typical Application Related Parts
pin FuncTions (DFN/GN) IN – (Pin 1/Pin 2):
Inverting Analog Input. gain control code. In parallel mode operation, if the data
SHDN (Pin 1 GN Package Only):
Shutdown Pin. The IC is in to DOUT (Pin 9) is from a voltage source greater than V+ shut down when SHDN is tied to V+. An internal current (Pin 12), then connect a resistor between the voltage source source pulls this pin to V– when floating. and DOUT to limit the current into Pin 9 to 5mA or less.
IN+ (Pin 2/Pin 3):
Noninverting Analog Input.
DGND (Pin 8/Pin 10):
Digital Ground.
V– (Pin 3/Pin 4):
Negative Supply.
PARALLEL_SERIAL (Pin 9/Pin 11):
Interface Selection Input. When tied to V+, the interface is in parallel mode,
CS(D0) (Pin 4/Pin 6):
TTL Level Input. When in serial i.e., the PGA gain is defined by the parallel codes (D3 ~ control mode, this pin is the chip select input (active low); D0), i.e., CS(D0), DATA(D1), CLK(D2), and DOUT(D3). in parallel control mode, this pin is the LSB of the parallel When PARALLEL_SERIAL pin is tied to V–, the PGA gain gain control code. is set by the serial interface.
DIN(D1) (Pin 5/Pin 7):
TTL Level Input. When in serial
REF (Pin 10/Pin 13):
Voltage Reference for PGA output. control mode, this pin is the serial input data; in paral- lel mode, this pin is the second LSB of the parallel gain
OUT (Pin 11/Pin 15):
Amplifier Output. The typical current control code. sourcing/sinking of the OUT pin is 1mA. For minimum gain error, the load resistance should be 1k or greater
HOLD_THRU (Pin 5 GN Package Only):
TTL Level Input (refer to the Output Voltage Swing vs Output Current and for Parallel Control Mode. When HOLD_THRU is high, the Gain Error vs Load Resistance in the Typical Performance parallel data is latched in an internal D-latch. Characteristics section).
CLK(D2) (Pin 6/Pin 8):
TTL Level Input. When in serial
V+ (Pin 12/Pin 16):
Positive Supply. control mode, this pin is the clock of the serial interface; in parallel mode, this pin is the third LSB of the parallel
SENSE (Pin 14 GN Package Only):
Sense Pin. When the gain control code. PGA drives a low resistance load and the interconnect resistance between the OUT pin and the load is not neg-
DOUT(D3) (Pin 7/Pin 9):
TTL Level Input. When in serial ligible, tying the SENSE pin as close as possible to the control mode, this pin is the output of the serial data; in load can improve the gain accuracy. parallel mode, this pin is the MSB of the 4-bit parallel 6915fb 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Operation Typical Application Package Description Revision History Typical Application Related Parts
