Datasheet LTC3815 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management |
| Pages / Page | 42 / 3 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply … |
| Revision | B |
| File Format / Size | PDF / 3.0 Mb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the specified operating
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LTC3815
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Range l 2.25 5.5 V VOUT Output Voltage Programming Range l 0.4 72% of VIN V IQ VIN Supply Current Normal Mode VRUN_MSTR > 1V (Note 4) 5 8 mA Standby VRUN_STBY = 0V, VRUN_MSIR > 1V 120 200 µA Shutdown VRUN_MSTR = 0V, VSDA = VSCL ≥ VIN 1 µA VUVLO VIN Undervoltage Reset VIN Rising 2.05 2.15 2.25 V Hysterisis VIN Falling 0.2 V IREF Reference Current (Note 10) l 99.2 100 100.8 µA 99.5 100 100.5 µA ΔIREF,LINE Reference Current Line Regulation VIN = 2.5V to 5.5V (Note 10) l 0.05 0.2 %/V ΔVOUT,OFFSET Regulation Accuracy VREF = 1.5V (Notes 5, 10) l –0.5 0.5 % ΔVOUT,OFFSET = (VCC_SEN – VSS_SEN) – VREF ΔVOUT,MARGIN Maximum Margining Range –25 25 % Set Point Accuracy MFR_VOUT_COMMAND = –25% to l –0.5 0.5 % 25%, VREF = 1.5V (Note 5) Resolution 9 Bits LSD Step Size 0.1 % NL_VOUT DAC Nonlinearity ±1 LSB AEA Error Amplifier Open Loop Gain ITH = 1V (Note 5) 80 dB fBW Error Amp Gain Bandwidth Product (Note 6) 20 MHz RIN Differential Amplier Input Resistance Measured at VCC_SEN Pin 160 kΩ tSS Internal Soft-Start Time/VREF External CSS = Float 1 ms/V ICSLEW CSLEW Pull-Up Current VCSLEW = 0V –10 µA ILIM SW Valley Current Limit Sourcing (Note 8) l 5.5 6.5 7.5 A Sinking –6 A IRUN_STBY Regulator On Source Current VRUN_STBY = 0V –2.5 µA VRUN_MSTR Regulator On Threshold (Master Shutdown) Rising Edge 0.9 1 1.1 V Regulator On Hysterisis Falling Edge 0.1 V Regulator Power-Down Threshold IQ < 10μA 0.65 V VRUN_STBY Regulator On Threshold (Standby Mode) 0.7 1 1.2 V IASEL ASEL Programming Current 10 µA IPGFD PGFD Programming Current 10 µA ISS SS Current VSS = 0V 4 5 6 µA VIH,MARGIN MARGIN High Voltage 1.2 V VIL,MARGIN MARGIN Low Voltage 0.4 V IWP WP Pin Pull-Up Current WP = 0V 10 µA SRMARGIN Reference Slew Rate During Margin Change CSLEW = 1nF 0.1 %/ms CSLEW = OPEN 23 %/ms CSLEW = SVIN 10 %/µs tINIT Initialization Time Delay from Power Applied Until 1 2 ms VOUT Ramp Up
Oscillator and Power Switch
fOSC Oscillator Frequency RT = 25.5k l 0.85 1.0 1.15 MHz RT = SVIN 0.85 1.0 1.15 MHz VSYNC SYNC Level High 1.2 V SYNC Level Low 0.3 V Rev B For more information www.analog.com 3 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information PMBus Command Details Typical Applications Package Description Revision History Typical Application Related Parts
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Range l 2.25 5.5 V VOUT Output Voltage Programming Range l 0.4 72% of VIN V IQ VIN Supply Current Normal Mode VRUN_MSTR > 1V (Note 4) 5 8 mA Standby VRUN_STBY = 0V, VRUN_MSIR > 1V 120 200 µA Shutdown VRUN_MSTR = 0V, VSDA = VSCL ≥ VIN 1 µA VUVLO VIN Undervoltage Reset VIN Rising 2.05 2.15 2.25 V Hysterisis VIN Falling 0.2 V IREF Reference Current (Note 10) l 99.2 100 100.8 µA 99.5 100 100.5 µA ΔIREF,LINE Reference Current Line Regulation VIN = 2.5V to 5.5V (Note 10) l 0.05 0.2 %/V ΔVOUT,OFFSET Regulation Accuracy VREF = 1.5V (Notes 5, 10) l –0.5 0.5 % ΔVOUT,OFFSET = (VCC_SEN – VSS_SEN) – VREF ΔVOUT,MARGIN Maximum Margining Range –25 25 % Set Point Accuracy MFR_VOUT_COMMAND = –25% to l –0.5 0.5 % 25%, VREF = 1.5V (Note 5) Resolution 9 Bits LSD Step Size 0.1 % NL_VOUT DAC Nonlinearity ±1 LSB AEA Error Amplifier Open Loop Gain ITH = 1V (Note 5) 80 dB fBW Error Amp Gain Bandwidth Product (Note 6) 20 MHz RIN Differential Amplier Input Resistance Measured at VCC_SEN Pin 160 kΩ tSS Internal Soft-Start Time/VREF External CSS = Float 1 ms/V ICSLEW CSLEW Pull-Up Current VCSLEW = 0V –10 µA ILIM SW Valley Current Limit Sourcing (Note 8) l 5.5 6.5 7.5 A Sinking –6 A IRUN_STBY Regulator On Source Current VRUN_STBY = 0V –2.5 µA VRUN_MSTR Regulator On Threshold (Master Shutdown) Rising Edge 0.9 1 1.1 V Regulator On Hysterisis Falling Edge 0.1 V Regulator Power-Down Threshold IQ < 10μA 0.65 V VRUN_STBY Regulator On Threshold (Standby Mode) 0.7 1 1.2 V IASEL ASEL Programming Current 10 µA IPGFD PGFD Programming Current 10 µA ISS SS Current VSS = 0V 4 5 6 µA VIH,MARGIN MARGIN High Voltage 1.2 V VIL,MARGIN MARGIN Low Voltage 0.4 V IWP WP Pin Pull-Up Current WP = 0V 10 µA SRMARGIN Reference Slew Rate During Margin Change CSLEW = 1nF 0.1 %/ms CSLEW = OPEN 23 %/ms CSLEW = SVIN 10 %/µs tINIT Initialization Time Delay from Power Applied Until 1 2 ms VOUT Ramp Up
Oscillator and Power Switch
fOSC Oscillator Frequency RT = 25.5k l 0.85 1.0 1.15 MHz RT = SVIN 0.85 1.0 1.15 MHz VSYNC SYNC Level High 1.2 V SYNC Level Low 0.3 V Rev B For more information www.analog.com 3 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information PMBus Command Details Typical Applications Package Description Revision History Typical Application Related Parts
