Datasheet ADP5041 (Analog Devices) - 37
| Manufacturer | Analog Devices |
| Description | Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset |
| Pages / Page | 40 / 37 — Data Sheet. ADP5041. PCB LAYOUT GUIDELINES. SUGGESTED LAYOUT. 0.5. 1.0. … |
| Revision | B |
| File Format / Size | PDF / 3.7 Mb |
| Document Language | English |
Data Sheet. ADP5041. PCB LAYOUT GUIDELINES. SUGGESTED LAYOUT. 0.5. 1.0. 1.5. 2.0. 2.5. 3.0. 3.5. 4.0. 4.5. 5.0. 5.5. 6.0. 6.5. 7.0. PPL. VOUT3. GPL. C3 – 1µF
Text Version of Document
link to page 37
Data Sheet ADP5041 PCB LAYOUT GUIDELINES
Poor layout can affect ADP5041 performance, causing electro-
SUGGESTED LAYOUT
magnetic interference (EMI) and electromagnetic compatibility See Figure 114 for an example layout. (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. • Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. • Maximize the size of ground metal on the component side to help with thermal dissipation. • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 mm PPL VOUT3 GPL 0.5 C3 – 1µF C6 – 2.2µF GPL 10V/XR5 6.3V/XR5 0402 0402 1.0
P in
3 3
1
TO 3 R 3 FILT S EN N UT FB 1.5 30Ω nR VI O V 0402 PPL PPL PPL 2.0 AVIN MR 2.5 VIN1 WDI GPL GPL 3.0 C1 – 4.7µF SW AGND VTHR 10V/XR5 0603 L1 – 1µH 3.5 0603 GPL GPL PGND MODE 4.0 ADP5041 EN1 EN2 L L P P G G 4.5 L L P P G G 1 2 1 2 UT N UT 2 O FB VI O V V FB 5.0 VIAS LEGEND: C4 – 10µF PPL = POWER PLANE (+4V) 6.3V/XR5 5.5 0603 GPL = GROUND PLANE C2 – 1µF C5 – 2.2µF 10V/XR5 6.3V/XR5 TOP LAYER 0402 0402 6.0 VOUT1 2ND LAYER PPL VOUT2
102
mm
09652- Figure 114. Suggested Board Layout Rev. A | Page 37 of 40 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog Input APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITOR Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Threshold Setting Resistors Watchdog Input Current Negative-Going Transients at the Monitored Rail Watchdog Software Considerations POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADP5041 PCB LAYOUT GUIDELINES
Poor layout can affect ADP5041 performance, causing electro-
SUGGESTED LAYOUT
magnetic interference (EMI) and electromagnetic compatibility See Figure 114 for an example layout. (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. • Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. • Maximize the size of ground metal on the component side to help with thermal dissipation. • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 mm PPL VOUT3 GPL 0.5 C3 – 1µF C6 – 2.2µF GPL 10V/XR5 6.3V/XR5 0402 0402 1.0
P in
3 3
1
TO 3 R 3 FILT S EN N UT FB 1.5 30Ω nR VI O V 0402 PPL PPL PPL 2.0 AVIN MR 2.5 VIN1 WDI GPL GPL 3.0 C1 – 4.7µF SW AGND VTHR 10V/XR5 0603 L1 – 1µH 3.5 0603 GPL GPL PGND MODE 4.0 ADP5041 EN1 EN2 L L P P G G 4.5 L L P P G G 1 2 1 2 UT N UT 2 O FB VI O V V FB 5.0 VIAS LEGEND: C4 – 10µF PPL = POWER PLANE (+4V) 6.3V/XR5 5.5 0603 GPL = GROUND PLANE C2 – 1µF C5 – 2.2µF 10V/XR5 6.3V/XR5 TOP LAYER 0402 0402 6.0 VOUT1 2ND LAYER PPL VOUT2
102
mm
09652- Figure 114. Suggested Board Layout Rev. A | Page 37 of 40 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog Input APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITOR Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Threshold Setting Resistors Watchdog Input Current Negative-Going Transients at the Monitored Rail Watchdog Software Considerations POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE