Datasheet LT3692A (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Monolithic Dual Tracking 3.5A Step-Down Switching Regulator |
| Pages / Page | 42 / 10 — pin FuncTions SHDN1/SHDN2:. SW1/SW2:. VC1/VC2:. SS1/SS2:. VIN1:. IN2:. … |
| File Format / Size | PDF / 742 Kb |
| Document Language | English |
pin FuncTions SHDN1/SHDN2:. SW1/SW2:. VC1/VC2:. SS1/SS2:. VIN1:. IN2:. CLKOUT:. OUT1/VOUT2:
Model Line for this Datasheet
Text Version of Document
LT3692A
pin FuncTions SHDN1/SHDN2:
The shutdown pin is used to control each
SW1/SW2:
The SW pin is the emitter of the internal power channel’s operation. In addition to controlling channel 1, NPN. At switch off, the inductor will drive this pin below the SHDN1 pin also activates control circuitry for both ground with a high dV/dt. An external Schottky catch channels and must be present for channel 2 to operate. diode to ground, close to the SW pin and respective VIN When SHDN1 is below its threshold, switching on both decoupling capacitor’s ground, must be used to prevent channels is halted. Further reducing the SHDN1 voltage this pin from excessive negative voltages. to 0.6V reduces the quiescent current to a typical value
T
of 6µA Independent channel UVLO can be programmed
J:
The TJ pin outputs a voltage proportional to junction temperature. The pin is 250mV for 25°C and has a slope by connecting the SHDN pin to an input voltage divider. of 10mV/°C. See the Applications Information section for See the Applications Information section for more infor- more information. mation. If the shutdown features are not used, the SHDN pin should be tied to VIN.
VC1/VC2:
The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is
SS1/SS2:
Current flowing out the SS pin into an external normally used for frequency compensation, but can also capacitor defines the rise time of the output voltage. When be used as a current clamp or control loop override. If the SS pin is lower than the 0.806V reference, the feedback the error amplifier drives V is regulated to the SS voltage. When the SS pin exceeds C above the maximum switch current level, a voltage clamp activates. This indicates that the reference voltage, the output will regulate the FB pin the output is overloaded and current is pulled from the SS voltage to 0.806V and the SS pin will continue to rise until pin reducing the regulation point. its clamp voltage. During an output overload, the VC pin is driven above the maximum switch current level activating
VIN1:
The VIN1 pin powers the internal control circuitry for its voltage clamp. When the VC clamp is activated, the SS both channels and is monitored by overvoltage/undervolt- pin is discharged until the output reaches a regulation point age lockout comparators. The VIN1 pin is also connected that the maximum output current can maintain. When the to the collector of channel 1’s on-chip power NPN switch. overload condition is removed, the output soft starts from The VIN1 pin has high dI/dt edges and must be decoupled that voltage. In the case of a SHDN or thermal shutdown to ground close to the pin of the device. event, a power on reset latch ensures the capacitors on
V
both channels are fully discharged before either is released.
IN2:
The VIN2 pin powers the output stage for channel 2 and is monitored by overvoltage/undervoltage lockout Connecting both SS pins together ensures the outputs comparators. V track together. IN1 voltage must be greater than typically 2.8V for VIN2 operation. The VIN2 pin is also the collector
CLKOUT:
The CLKOUT pin generates a square wave of 0V of channel 2’s on-chip power NPN switch. The VIN2 pin to 2.5V which is synchronized to the internal oscillator. If has high dI/dt edges and must be decoupled to ground the switching frequency is set by an external resistor the close to the pin of the device. resultant clock duty cycle will be 50%. If the RT/SYNC pin
V
is driven by an external clock source, the resultant CLKOUT
OUT1/VOUT2:
The VOUT pin is the output to the internal sense resistor that measures current flowing in the induc- duty cycle will mirror the external source. tor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset disabling the output switch. Bias current flows out of the VOUT pin. 3692afc 10 For more information www.linear.com/3692A Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions SHDN1/SHDN2:
The shutdown pin is used to control each
SW1/SW2:
The SW pin is the emitter of the internal power channel’s operation. In addition to controlling channel 1, NPN. At switch off, the inductor will drive this pin below the SHDN1 pin also activates control circuitry for both ground with a high dV/dt. An external Schottky catch channels and must be present for channel 2 to operate. diode to ground, close to the SW pin and respective VIN When SHDN1 is below its threshold, switching on both decoupling capacitor’s ground, must be used to prevent channels is halted. Further reducing the SHDN1 voltage this pin from excessive negative voltages. to 0.6V reduces the quiescent current to a typical value
T
of 6µA Independent channel UVLO can be programmed
J:
The TJ pin outputs a voltage proportional to junction temperature. The pin is 250mV for 25°C and has a slope by connecting the SHDN pin to an input voltage divider. of 10mV/°C. See the Applications Information section for See the Applications Information section for more infor- more information. mation. If the shutdown features are not used, the SHDN pin should be tied to VIN.
VC1/VC2:
The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is
SS1/SS2:
Current flowing out the SS pin into an external normally used for frequency compensation, but can also capacitor defines the rise time of the output voltage. When be used as a current clamp or control loop override. If the SS pin is lower than the 0.806V reference, the feedback the error amplifier drives V is regulated to the SS voltage. When the SS pin exceeds C above the maximum switch current level, a voltage clamp activates. This indicates that the reference voltage, the output will regulate the FB pin the output is overloaded and current is pulled from the SS voltage to 0.806V and the SS pin will continue to rise until pin reducing the regulation point. its clamp voltage. During an output overload, the VC pin is driven above the maximum switch current level activating
VIN1:
The VIN1 pin powers the internal control circuitry for its voltage clamp. When the VC clamp is activated, the SS both channels and is monitored by overvoltage/undervolt- pin is discharged until the output reaches a regulation point age lockout comparators. The VIN1 pin is also connected that the maximum output current can maintain. When the to the collector of channel 1’s on-chip power NPN switch. overload condition is removed, the output soft starts from The VIN1 pin has high dI/dt edges and must be decoupled that voltage. In the case of a SHDN or thermal shutdown to ground close to the pin of the device. event, a power on reset latch ensures the capacitors on
V
both channels are fully discharged before either is released.
IN2:
The VIN2 pin powers the output stage for channel 2 and is monitored by overvoltage/undervoltage lockout Connecting both SS pins together ensures the outputs comparators. V track together. IN1 voltage must be greater than typically 2.8V for VIN2 operation. The VIN2 pin is also the collector
CLKOUT:
The CLKOUT pin generates a square wave of 0V of channel 2’s on-chip power NPN switch. The VIN2 pin to 2.5V which is synchronized to the internal oscillator. If has high dI/dt edges and must be decoupled to ground the switching frequency is set by an external resistor the close to the pin of the device. resultant clock duty cycle will be 50%. If the RT/SYNC pin
V
is driven by an external clock source, the resultant CLKOUT
OUT1/VOUT2:
The VOUT pin is the output to the internal sense resistor that measures current flowing in the induc- duty cycle will mirror the external source. tor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset disabling the output switch. Bias current flows out of the VOUT pin. 3692afc 10 For more information www.linear.com/3692A Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
