Datasheet ADP5043 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionMicro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
Pages / Page30 / 6 — ADP5043. Data Sheet. Parameter. Symbol. Test Conditions/Comments. Min. …
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Document LanguageEnglish

ADP5043. Data Sheet. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit

ADP5043 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit

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ADP5043 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
REGULATION Line Regulation ∆VOUT2/∆VIN2 VIN2= (VOUT2 + 0.5 V) to 5.5 V −0.03 +0.03 %/V IOUT2 = 1 mA TJ = −40°C to +125°C Load Regulation1 ∆VOUT2/∆IOUT2 IOUT2 = 1 mA to 200 mA 0.002 %/mA IOUT2 = 1 mA to 200 mA 0.0075 %/mA TJ = −40°C to +125°C DROPOUT VOLTAGE2 VDROPOUT VOUT2 = 3.3 V IOUT2 = 10 mA 4 mV IOUT2 = 10 mA, TJ = −40°C to +125°C 5 mV IOUT2 = 200 mA 60 mV IOUT2 = 200 mA, TJ = −40°C to +125°C 100 mV ACTIVE PULL-DOWN RPDLDO EN2 = 0 V 600 Ω START-UP TIME TSTART-UP VOUT2 = 3.3 V 85 µs CURRENT-LIMIT THRESHOLD3 ILIMIT TJ = −40°C to +125°C 335 470 mA OUTPUT NOISE OUTLDONOISE 10 Hz to 100 kHz, VIN2 = 5 V, 123 µV rms VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V, 110 µV rms VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V, 59 µV rms VOUT2 = 1.5 V POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, 66 dB IOUT = 100 mA 100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, 57 dB IOUT = 100 mA 1 MHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, 60 dB IOUT = 100 mA 1 Based on an end-point calculation using 1 mA and 100 mA loads. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT CAPACITANCE (BUCK)1 CMIN1 TJ = −40°C to +125°C 7 40 µF MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO) CMIN2 TJ = −40°C to +125°C 0.70 µF CAPACITOR ESR RESR TJ = −40°C to +125°C 0.001 1 Ω 1 The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. 2 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck. Rev. B | Page 6 of 30 Document Outline FEATURES GENERAL DESCRIPTION HIGH LEVEL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog 1 Input Watchdog 2 Input Watchdog Status Indicator APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Watchdog 1 Input Current Negative-Going VCC Transients Watchdog Software Considerations PCB LAYOUT GUIDELINES POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT BILL OF MATERIALS APPLICATION DIAGRAM FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
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