Datasheet ADP2140 (Analog Devices) - 5

Data Sheet ADP2140 ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θ
Table 3.
JA) of the package is based on modeling and calculation using a 4-layer board. The
Parameter Rating
junction-to-ambient thermal resistance is highly dependent on VIN1, VIN2 to PGND, AGND −0.3 V to +6.5 V the application and board layout. In applications where high VOUT2 to PGND, AGND −0.3 V to V IN2 maximum power dissipation exists, close attention to thermal SW to PGND, AGND −0.3 V to V IN1 board design is required. The value of θJA may vary, depending FB to PGND, AGND −0.3 V to +6.5 V on PCB material, layout, and environmental conditions. The PG to PGND, AGND −0.3 V to +6.5 V specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit EN1, EN2 to PGND, AGND −0.3 V to +6.5 V board. Refer to JESD 51-7 for detailed information on the board Storage Temperature Range −65°C to +150°C construction. Operating Ambient Temperature Range −40°C to +85°C For more information, see AN-772 Application Note, A Design Operating Junction Temperature Range −40°C to +125°C and Manufacturing Guide for the Lead Frame Chip Scale Package Soldering Conditions JEDEC J-STD-020 (LFCSP). Stresses above those listed under Absolute Maximum Ratings Ψ may cause permanent damage to the device. This is a stress JB is the junction-to-board thermal characterization parameter with units of °C/W. Ψ rating only; functional operation of the device at these or any JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal maximum rating conditions for extended periods may affect resistances. Ψ device reliability.

JB measures the component power flowing through multiple thermal paths rather than a single path, as in thermal
THERMAL DATA
resistance, θJB. Therefore, ΨJB thermal paths include convection Absolute maximum ratings apply individually only, not in com- from the top of the package as wel as radiation from the package, bination. The ADP2140 can be damaged when the junction factors that make ΨJB more useful in real-world applications. temperature limits are exceeded. Monitoring ambient temperature Maximum junction temperature (TJ) is calculated from the does not guarantee that T board temperature (T J is within the specified temperature B) and power dissipation (PD) using the limits. In applications with high power dissipation and poor formula thermal resistance, the maximum ambient temperature may TJ = TB + (PD × ΨJB) need to be derated. Refer to JESD51-8 and JESD51-12 for more detailed In applications with moderate power dissipation and low information about ΨJB. printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as
THERMAL RESISTANCE
the junction temperature is within specification limits. The θ junction temperature (T JA and ΨJB are specified for the worst-case conditions, that is, a J) of the device is dependent on the device soldered in a circuit board for surface-mount packages. ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the
Table 4. Thermal Resistance
package (θJA).
Package Type θ Ψ Unit JA JB
Maximum junction temperature (T 10-Lead 3 mm × 3 mm LFCSP 35.3 16.9 °C/W J) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula
ESD CAUTION
TJ = TA + (PD × θJA) Rev. A | Page 5 of 32 Document Outline Features Applications General Description Typical Application Circuits Revision History Specifications Recommended Specifications: Capacitors and Inductor Pin Configuration and Function Descriptions Typical Performance Characteristics Buck Output LDO Output Theory of Operation Buck Section Control Scheme PWM Operation PSM Operation Pulse Skipping Threshold Selected Features Short-Circuit Protection Undervoltage Lockout Thermal Protection Soft Start Current Limit Power-Good Pin LDO Section Applications Information Power Sequencing Power-Good Function External Component Selection Selecting the Inductor Output Capacitor Input Capacitor Efficiency Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses Recommended Buck External Components LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties LDO as a Postregulator to Reduce Buck Output Noise Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide