Datasheet ADP2116 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator |
| Pages / Page | 36 / 10 — ADP2116. Data Sheet. 250. 330. fSW = 300kHz. 225. SW = 600kHz. fSW = … |
| Revision | B |
| File Format / Size | PDF / 2.9 Mb |
| Document Language | English |
ADP2116. Data Sheet. 250. 330. fSW = 300kHz. 225. SW = 600kHz. fSW = 1.2MHz. 320. 200. s) (n. 310. 175. IME. N 150. (k 300. M O. f SW. 125. IMU N. 290. MI 100. 280
Model Line for this Datasheet
Text Version of Document
ADP2116 Data Sheet 250 330 fSW = 300kHz f 225 SW = 600kHz fSW = 1.2MHz 320 200 s) (n 310 175 IME z) T H N 150 (k 300 M O f SW 125 IMU N 290 MI 100 280 75 50 270 2.5 3.0 3.5 4.0 4.5 5.0 5.5
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2.5 3.0 3.5 4.0 4.5 5.0 5.5
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43 08 08 Figure 14. Minimum On Time, Open Loop, Includes Dead Time Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
350 660 fSW = 300kHz 330 fSW = 600kHz fSW = 1.2MHz 640 310 ) 290 (ns 620 270 TIME z) F F 250 (kH 600 M O 230 f SW IMU 580 IN 210 M 190 560 170 150 540 2.5 3.0 3.5 4.0 4.5 5.0 5.5
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2.5 3.0 3.5 4.0 4.5 5.0 5.5
8 01 01 6- 6-
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43 08 08 Figure 15. Minimum Off Time, Open Loop, Includes Dead Time Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
120 50 +125°C +125°C +115°C 45 +115°C +85°C +85°C 100 +25C +25C –40°C 40 –40°C ) 35 80 ) Ω Ω (m (m 30 N N DSO 60 DSO 25 R R S S O O 20 PM 40 NM 15 10 20 5 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
9 16
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0 01 6- 6-
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43 08 08 Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires Rev. B | Page 10 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LINE AND LOAD REGULATION SUPPLY CURRENT LOAD TRANSIENT RESPONSE BASIC FUNCTIONALITY BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION AND THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
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2.5 3.0 3.5 4.0 4.5 5.0 5.5
17 01 0 6- 6-
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43
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43 08 08 Figure 14. Minimum On Time, Open Loop, Includes Dead Time Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
350 660 fSW = 300kHz 330 fSW = 600kHz fSW = 1.2MHz 640 310 ) 290 (ns 620 270 TIME z) F F 250 (kH 600 M O 230 f SW IMU 580 IN 210 M 190 560 170 150 540 2.5 3.0 3.5 4.0 4.5 5.0 5.5
5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
8 01 01 6- 6-
VIN (V)
43
VIN (V)
43 08 08 Figure 15. Minimum Off Time, Open Loop, Includes Dead Time Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
120 50 +125°C +125°C +115°C 45 +115°C +85°C +85°C 100 +25C +25C –40°C 40 –40°C ) 35 80 ) Ω Ω (m (m 30 N N DSO 60 DSO 25 R R S S O O 20 PM 40 NM 15 10 20 5 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
9 16
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0 01 6- 6-
VIN (V)
43
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43 08 08 Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires Rev. B | Page 10 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LINE AND LOAD REGULATION SUPPLY CURRENT LOAD TRANSIENT RESPONSE BASIC FUNCTIONALITY BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION AND THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
