Datasheet ADP5022 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO |
| Pages / Page | 28 / 1 — Dual 3 MHz, 600 mA Buck. Regulator with 150 mA LDO. ADP5022. FEATURES. … |
| Revision | C |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Dual 3 MHz, 600 mA Buck. Regulator with 150 mA LDO. ADP5022. FEATURES. GENERAL DESCRIPTION. Input voltage range: 2.4 V to 5.5 V
Model Line for this Datasheet
Text Version of Document
Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO ADP5022 FEATURES GENERAL DESCRIPTION Input voltage range: 2.4 V to 5.5 V
The ADP5022 is a micro power management unit (micro PMU)
Tiny 16-ball, 2 mm × 2 mm WLCSP package
that combines two high performance buck regulators and a low
Overcurrent and thermal protection
dropout regulator (LDO) in a tiny 16-ball 2.08 mm × 2.08 mm
Soft start
WLCSP to meet demanding performance and board space
Factory programmable undervoltage lockout on VDDA
requirements.
system supply of either 2.2 V or 3.9 V
The high switching frequency of the buck regulators enables
Factory programmable default output voltages for all
tiny multilayer external components and minimizes the board
3 channels
space required. When the MODE pin is set high, the buck reg-
Buck1 and Buck2 key specifications
ulators operate in forced PWM mode. When the MODE pin is
Current mode architecture for excellent transient response
set low, the buck regulators automatically switch operating
3 MHz operating frequency
modes, depending on the load current level. At higher output
Uses tiny multilayer inductors and capacitors
loads, the buck regulators operate in PWM mode. When the
Forced PWM and auto PWM/PSM modes
load current falls below a predefined threshold, the regulators
Out-of-phase operation for reduced input filtering
operate in power save mode (PSM), improving the light-load
100% duty cycle low dropout mode
efficiency.
24 μA typical quiescent current per channel, no switching LDO key specifications
The two bucks operate out-of-phase to reduce the input
Stable with 1 μF ceramic output capacitors
capacitor requirement and noise.
High PSRR
The low quiescent current, low dropout voltage, and wide input
60 dB up to 10 KHz
voltage range of the ADP5022 LDO extends the battery life of
Low output noise
portable devices. The LDO maintains power supply rejection
65 μV rms output noise at VOUT3 = 3.3 V
greater than 60 dB for frequencies as high as 10 kHz while
Low dropout voltage: 150 mV @ 150 mA load
operating with a low headroom voltage.
11 μA typical ground current at no load
Each regulator in the ADP5022 has a dedicated, independent
APPLICATIONS
enable pin. A high voltage level applied to the enable pin activates
USB devices
the respective regulator. The default output voltages are factory
Handheld products
programmable and can be set to a wide range of options.
Multivoltage power for processors, ASICS, FPGAs, and RF chipsets ADP5022 L1 1µH COUT_3 V VIN1 SW1 V IN = 2.4V OUT1 @ TO 5.5V 600mA C2 ON BUCK1 VOUT1 C4 C3 C4 4.7µF EN1 OFF PGND1 10µF EN_BK1 MODE PWM MODE C1 C2 PWM/PSM VIN2 L2 1µH C3 MODE SW2 VOUT2 @ 4.7µF ON BUCK2 VOUT2 600mA C5 5.0mm OFF EN2 PGND2 10µF EN_BK2 VDDA R R O O C1 VIN3 T T C C 1µF VOUT3 V LDO1 OUT3 @ U U ON 150mA D D IN IN OFF EN3 C6 EN_LDO1 1µF L1 COUT_1 COUT_2
61 01 0 0 3-
AGND
3- 25 25
4.7mm
08 08 Figure 1. Typical Applications Circuit Figure 2. Typical PCB Layout
Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK1 AND BUCK2 SPECIFICATIONS LDO SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Enable/Shutdown Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION LDO Undervoltage Lockout APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PCB LAYOUT GUIDELINES EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
The ADP5022 is a micro power management unit (micro PMU)
Tiny 16-ball, 2 mm × 2 mm WLCSP package
that combines two high performance buck regulators and a low
Overcurrent and thermal protection
dropout regulator (LDO) in a tiny 16-ball 2.08 mm × 2.08 mm
Soft start
WLCSP to meet demanding performance and board space
Factory programmable undervoltage lockout on VDDA
requirements.
system supply of either 2.2 V or 3.9 V
The high switching frequency of the buck regulators enables
Factory programmable default output voltages for all
tiny multilayer external components and minimizes the board
3 channels
space required. When the MODE pin is set high, the buck reg-
Buck1 and Buck2 key specifications
ulators operate in forced PWM mode. When the MODE pin is
Current mode architecture for excellent transient response
set low, the buck regulators automatically switch operating
3 MHz operating frequency
modes, depending on the load current level. At higher output
Uses tiny multilayer inductors and capacitors
loads, the buck regulators operate in PWM mode. When the
Forced PWM and auto PWM/PSM modes
load current falls below a predefined threshold, the regulators
Out-of-phase operation for reduced input filtering
operate in power save mode (PSM), improving the light-load
100% duty cycle low dropout mode
efficiency.
24 μA typical quiescent current per channel, no switching LDO key specifications
The two bucks operate out-of-phase to reduce the input
Stable with 1 μF ceramic output capacitors
capacitor requirement and noise.
High PSRR
The low quiescent current, low dropout voltage, and wide input
60 dB up to 10 KHz
voltage range of the ADP5022 LDO extends the battery life of
Low output noise
portable devices. The LDO maintains power supply rejection
65 μV rms output noise at VOUT3 = 3.3 V
greater than 60 dB for frequencies as high as 10 kHz while
Low dropout voltage: 150 mV @ 150 mA load
operating with a low headroom voltage.
11 μA typical ground current at no load
Each regulator in the ADP5022 has a dedicated, independent
APPLICATIONS
enable pin. A high voltage level applied to the enable pin activates
USB devices
the respective regulator. The default output voltages are factory
Handheld products
programmable and can be set to a wide range of options.
Multivoltage power for processors, ASICS, FPGAs, and RF chipsets ADP5022 L1 1µH COUT_3 V VIN1 SW1 V IN = 2.4V OUT1 @ TO 5.5V 600mA C2 ON BUCK1 VOUT1 C4 C3 C4 4.7µF EN1 OFF PGND1 10µF EN_BK1 MODE PWM MODE C1 C2 PWM/PSM VIN2 L2 1µH C3 MODE SW2 VOUT2 @ 4.7µF ON BUCK2 VOUT2 600mA C5 5.0mm OFF EN2 PGND2 10µF EN_BK2 VDDA R R O O C1 VIN3 T T C C 1µF VOUT3 V LDO1 OUT3 @ U U ON 150mA D D IN IN OFF EN3 C6 EN_LDO1 1µF L1 COUT_1 COUT_2
61 01 0 0 3-
AGND
3- 25 25
4.7mm
08 08 Figure 1. Typical Applications Circuit Figure 2. Typical PCB Layout
Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK1 AND BUCK2 SPECIFICATIONS LDO SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Enable/Shutdown Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION LDO Undervoltage Lockout APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PCB LAYOUT GUIDELINES EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
