Datasheet ADP5020 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Power Management Unit for Imaging Modules |
| Pages / Page | 28 / 4 — ADP5020. SPECIFICATIONS. Table 1. Parameter Symbol. Conditions. Min. Typ. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADP5020. SPECIFICATIONS. Table 1. Parameter Symbol. Conditions. Min. Typ. Max. Unit
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ADP5020 SPECIFICATIONS
TJ = −40°C to +125°C, VDDx = 3.6 V, VDD_IO = 1.8 V, unless otherwise noted.
Table 1. Parameter Symbol Conditions Min Typ Max Unit
OPERATING RANGE VDDx Operating Voltage Range VDD 2.4 5.5 V Logic I/O Operating Voltage Range1 VDD_IO 1.7 3.6 V EN, SDA, SCL CHARACTERISTICS Low Level Input Voltage VIL 0.3 × VDD_IO V High Level Input Voltage VIH 0.7 × VDD_IO V INPUT LOGIC CURRENT ILK Internal pull-down, 1 MΩ −1 +6 μA XSHTDN, EN/GPIO Low Level Output Voltage VOL IRST = +3 mA 0.2 × VDD_IO V High Level Output Voltage VOH IRST = −3 mA 0.8 × VDD_IO V OUTPUT LOGIC LEAKAGE CURRENT ILK 1 μA UNDERVOLTAGE LOCKOUT THRESHOLD Falling VUVLOF Referenced to VDDA 1.8 2.0 V Rising VUVLOR Referenced to VDDA 2.2 2.4 V POWER-ON RESET THRESHOLD Falling VPORF Referenced to VDDA 1.0 1.4 V Rising VPORR Referenced to VDDA 1.6 1.7 V UVLO GLITCH DEBOUNCE TIME VDD > POR levels 50 μs SHUTDOWN OUTPUT DURATION2 tXSHTDN XSHTDN line driven low 1 ms POWER GOOD (POK) ACTIVATION DELAY TIME3 EN to First Regulator tREG1 5 ms First to Second Regulator tREG2 5 ms Second to Third Regulator tREG3 5 ms NO LOAD CURRENT CHARACTERISTICS Standby Current IQ(STNBY) EN = 0 1 5 μA Lockout Current ILOCK EN = 0, VDDA < VUVLOF 1 1 μA Operating Quiescent Current, Switching4 IQ ILOAD = 0 mA 10 15 mA THERMAL CHARACTERISTICS
Thermal Shutdown, TJ Rising TSD
150
°C Thermal Shutdown Hysteresis
30
°C HOUSEKEEPING BLOCK
Power Good Threshold VPG
70 80 90 % 1 The VDD_IO voltage must be less than or equal to the level on the VDDx supply lines. 2 Shutdown output duration is automatic when using the EN pin. To get this delay when using I2C, FORCE_XS must be set to 1. 3 Activation delays apply only when the device is activated through the EN pin or the EN_ALL bit (Address 0x03[4]); the sequencer controls the turning on of the regulators. 4 The quiescent current is calculated as though all regulators are powered up. Rev. 0 | Page 4 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE
ADP5020 SPECIFICATIONS
TJ = −40°C to +125°C, VDDx = 3.6 V, VDD_IO = 1.8 V, unless otherwise noted.
Table 1. Parameter Symbol Conditions Min Typ Max Unit
OPERATING RANGE VDDx Operating Voltage Range VDD 2.4 5.5 V Logic I/O Operating Voltage Range1 VDD_IO 1.7 3.6 V EN, SDA, SCL CHARACTERISTICS Low Level Input Voltage VIL 0.3 × VDD_IO V High Level Input Voltage VIH 0.7 × VDD_IO V INPUT LOGIC CURRENT ILK Internal pull-down, 1 MΩ −1 +6 μA XSHTDN, EN/GPIO Low Level Output Voltage VOL IRST = +3 mA 0.2 × VDD_IO V High Level Output Voltage VOH IRST = −3 mA 0.8 × VDD_IO V OUTPUT LOGIC LEAKAGE CURRENT ILK 1 μA UNDERVOLTAGE LOCKOUT THRESHOLD Falling VUVLOF Referenced to VDDA 1.8 2.0 V Rising VUVLOR Referenced to VDDA 2.2 2.4 V POWER-ON RESET THRESHOLD Falling VPORF Referenced to VDDA 1.0 1.4 V Rising VPORR Referenced to VDDA 1.6 1.7 V UVLO GLITCH DEBOUNCE TIME VDD > POR levels 50 μs SHUTDOWN OUTPUT DURATION2 tXSHTDN XSHTDN line driven low 1 ms POWER GOOD (POK) ACTIVATION DELAY TIME3 EN to First Regulator tREG1 5 ms First to Second Regulator tREG2 5 ms Second to Third Regulator tREG3 5 ms NO LOAD CURRENT CHARACTERISTICS Standby Current IQ(STNBY) EN = 0 1 5 μA Lockout Current ILOCK EN = 0, VDDA < VUVLOF 1 1 μA Operating Quiescent Current, Switching4 IQ ILOAD = 0 mA 10 15 mA THERMAL CHARACTERISTICS
Thermal Shutdown, TJ Rising TSD
150
°C Thermal Shutdown Hysteresis
30
°C HOUSEKEEPING BLOCK
Power Good Threshold VPG
70 80 90 % 1 The VDD_IO voltage must be less than or equal to the level on the VDDx supply lines. 2 Shutdown output duration is automatic when using the EN pin. To get this delay when using I2C, FORCE_XS must be set to 1. 3 Activation delays apply only when the device is activated through the EN pin or the EN_ALL bit (Address 0x03[4]); the sequencer controls the turning on of the regulators. 4 The quiescent current is calculated as though all regulators are powered up. Rev. 0 | Page 4 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE
