Datasheet LTC3562 (Analog Devices) - 13
| Manufacturer | Analog Devices |
| Description | I2C Quad Synchronous Step-Down DC/DC Regulator 2 x 600mA, 2 x 400mA |
| Pages / Page | 20 / 13 — OPERATION. Figure 3. Bit Assignments. Figure 4. Timing Parameters. Table … |
| File Format / Size | PDF / 258 Kb |
| Document Language | English |
OPERATION. Figure 3. Bit Assignments. Figure 4. Timing Parameters. Table 1. Write Word Protocol Used by the LTC3562
Model Line for this Datasheet
Text Version of Document
LTC3562
OPERATION
SUB-ADDRESS DATA BYTE ADDRESS WR 1 1 0 0 1 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP SDA 1 1 0 0 1 0 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 7 6 5 4 3 2 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3562 F03
Figure 3. Bit Assignments
SDA tSU, DAT tSU, STA tBUF tLOW tHD, DAT tHD, STA tSU, STO 3562 F04 SCL tHD, STA tHIGH tSP START REPEATED START STOP START tr tf CONDITION CONDITION CONDITION CONDITION
Figure 4. Timing Parameters Table 1. Write Word Protocol Used by the LTC3562
1 7 1 1 8 1 8 1 1 S Slave Address WR A *Sub-Address A Data Byte A P** S = Start Condition, WR = Write Bit = 0, A = Acknowledge, P = Stop Condition * The sub-address uses only the fi rst four most signifi cant bits, A7, A6, A5, and A4, for sub-addressing. The two least signifi cant bits, A1 and A0, are used to program the regulator operating mode. **Stop can be delayed until all of the data registers have been written.
Table 2. Sub-Address and Data Byte Mapping SUB-ADDRESS BYTE DATA BYTE
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 PROGRAM PROGRAM PROGRAM PROGRAM NOT USED REGULATOR ENABLE DAC CODE R600A R400A R600B R400B OPERATING REGULATOR (See Tables 4, 5 and 6) MODE (SEE TABLE 3) 3562fa 13
OPERATION
SUB-ADDRESS DATA BYTE ADDRESS WR 1 1 0 0 1 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP SDA 1 1 0 0 1 0 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 7 6 5 4 3 2 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3562 F03
Figure 3. Bit Assignments
SDA tSU, DAT tSU, STA tBUF tLOW tHD, DAT tHD, STA tSU, STO 3562 F04 SCL tHD, STA tHIGH tSP START REPEATED START STOP START tr tf CONDITION CONDITION CONDITION CONDITION
Figure 4. Timing Parameters Table 1. Write Word Protocol Used by the LTC3562
1 7 1 1 8 1 8 1 1 S Slave Address WR A *Sub-Address A Data Byte A P** S = Start Condition, WR = Write Bit = 0, A = Acknowledge, P = Stop Condition * The sub-address uses only the fi rst four most signifi cant bits, A7, A6, A5, and A4, for sub-addressing. The two least signifi cant bits, A1 and A0, are used to program the regulator operating mode. **Stop can be delayed until all of the data registers have been written.
Table 2. Sub-Address and Data Byte Mapping SUB-ADDRESS BYTE DATA BYTE
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 PROGRAM PROGRAM PROGRAM PROGRAM NOT USED REGULATOR ENABLE DAC CODE R600A R400A R600B R400B OPERATING REGULATOR (See Tables 4, 5 and 6) MODE (SEE TABLE 3) 3562fa 13