Datasheet LT3500 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller |
| Pages / Page | 28 / 8 — PIN FUNCTIONS. LDRV:. BST:. SW:. Exposed Pad:. FB:. LFB:. NC Pins (MSE … |
| File Format / Size | PDF / 331 Kb |
| Document Language | English |
PIN FUNCTIONS. LDRV:. BST:. SW:. Exposed Pad:. FB:. LFB:. NC Pins (MSE Package Only):
Model Line for this Datasheet
Text Version of Document
LT3500
PIN FUNCTIONS
Driving the RT/SYNC pin with an external clock signal
LDRV:
The LDRV pin is the emitter of an internal NPN that will synchronize the switch to the applied frequency. can be confi gured as an output of a linear regulator or as Synchronization occurs on the rising edge of the clock the drive for an external NPN high current regulator. Cur- signal after the clock signal is detected. Each rising clock rent fl ows out of the LDRV pin when the LFB pin voltage is edge initiates an oscillator ramp reset. A gain control loop below 0.8V. The LDRV pin has a typical maximum current servos the oscillator charging current to maintain a con- capability of 13mA. stant oscillator amplitude. Hence, the slope compensation
BST:
The BST pin provides a higher than V remains unchanged. If the clock signal is removed, the IN base drive to the power NPN to ensure a low switch drop. A compara- oscillator reverts to resistor mode and reapplies the 1V tor to V bias to the R IN imposes a minimum off time on the SW pin if T/SYNC pin after the synchronization detection the BST pin voltage drops too low. Forcing a SW off time circuitry times out. The clock source impedance should allows the boost capacitor to recharge. be set such that the current out of the RT/SYNC pin in resistor mode generates a frequency roughly equivalent
SW:
The SW pin is the emitter of the on-chip power NPN. to the synchronization frequency. Floating or holding the At switch off, the inductor will drive this pin below ground R with a high dV/dt. An external catch diode to ground, close T/SYNC pin above 1.1V will not damage the device, but will halt oscillation. to the SW pin and respective VIN decoupling capacitor’s
PG
ground, must be used to prevent this pin from excessive
:
The power good bar pin is an open-collector output negative voltages. that sinks current when the FB or LFB rises above 90% of its nominal regulating voltage.
Exposed Pad:
GND. The exposed pad is the only ground connection for the device. The exposed pad should be
FB:
The FB pin is the negative input to the switcher error soldered to a large copper area to reduce thermal resis- amplifi er. The output switches to regulate this pin to 0.8V tance. The GND pin also serves as small-signal ground. with respect to the exposed ground pad. Bias current For ideal operation all small-signal ground paths should fl ows out of the FB pin. connect to the GND pin at a single point, avoiding any
LFB:
The LFB pin is the negative input to the linear error high current ground returns. amplifi er. The LDRV pin servo’s to regulate this pin to 0.8V
NC Pins (MSE Package Only):
No Connection. The NC pins with respect to the exposed ground pad. Bias current fl ows are electrically isolated from the LT3500. The NC pins may out of the LFB pin. be connected to PCB traces to aid PCB layout. 3500fc 8
PIN FUNCTIONS
Driving the RT/SYNC pin with an external clock signal
LDRV:
The LDRV pin is the emitter of an internal NPN that will synchronize the switch to the applied frequency. can be confi gured as an output of a linear regulator or as Synchronization occurs on the rising edge of the clock the drive for an external NPN high current regulator. Cur- signal after the clock signal is detected. Each rising clock rent fl ows out of the LDRV pin when the LFB pin voltage is edge initiates an oscillator ramp reset. A gain control loop below 0.8V. The LDRV pin has a typical maximum current servos the oscillator charging current to maintain a con- capability of 13mA. stant oscillator amplitude. Hence, the slope compensation
BST:
The BST pin provides a higher than V remains unchanged. If the clock signal is removed, the IN base drive to the power NPN to ensure a low switch drop. A compara- oscillator reverts to resistor mode and reapplies the 1V tor to V bias to the R IN imposes a minimum off time on the SW pin if T/SYNC pin after the synchronization detection the BST pin voltage drops too low. Forcing a SW off time circuitry times out. The clock source impedance should allows the boost capacitor to recharge. be set such that the current out of the RT/SYNC pin in resistor mode generates a frequency roughly equivalent
SW:
The SW pin is the emitter of the on-chip power NPN. to the synchronization frequency. Floating or holding the At switch off, the inductor will drive this pin below ground R with a high dV/dt. An external catch diode to ground, close T/SYNC pin above 1.1V will not damage the device, but will halt oscillation. to the SW pin and respective VIN decoupling capacitor’s
PG
ground, must be used to prevent this pin from excessive
:
The power good bar pin is an open-collector output negative voltages. that sinks current when the FB or LFB rises above 90% of its nominal regulating voltage.
Exposed Pad:
GND. The exposed pad is the only ground connection for the device. The exposed pad should be
FB:
The FB pin is the negative input to the switcher error soldered to a large copper area to reduce thermal resis- amplifi er. The output switches to regulate this pin to 0.8V tance. The GND pin also serves as small-signal ground. with respect to the exposed ground pad. Bias current For ideal operation all small-signal ground paths should fl ows out of the FB pin. connect to the GND pin at a single point, avoiding any
LFB:
The LFB pin is the negative input to the linear error high current ground returns. amplifi er. The LDRV pin servo’s to regulate this pin to 0.8V
NC Pins (MSE Package Only):
No Connection. The NC pins with respect to the exposed ground pad. Bias current fl ows are electrically isolated from the LT3500. The NC pins may out of the LFB pin. be connected to PCB traces to aid PCB layout. 3500fc 8
