Datasheet LTC3670 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Monolithic 400mA Buck Regulator with Dual 150mA LDOs in 3mm × 2mm DFN |
| Pages / Page | 14 / 6 — PIN FUNCTIONS. SW (Pin 1):. LDO2_FB (Pin 8):. GND (Pin 2):. ENLDO1 (Pin … |
| Revision | A |
| File Format / Size | PDF / 401 Kb |
| Document Language | English |
PIN FUNCTIONS. SW (Pin 1):. LDO2_FB (Pin 8):. GND (Pin 2):. ENLDO1 (Pin 3):. LDO1_FB (Pin 9):. ENLDO2 (Pin 4):. LDO1 (Pin 10):
Model Line for this Datasheet
Text Version of Document
LTC3670
PIN FUNCTIONS SW (Pin 1):
Buck Regulator Switch Node Connection to In-
LDO2_FB (Pin 8):
Feedback Voltage Input for the Second ductor. This pin connects to the drains of the buck regulator’s Low Dropout Linear Regulator (LDO2). Typically, an ex- main PMOS and synchronous NMOS switches. ternal resistor divider feeds a fraction of the LDO2 output
GND (Pin 2):
Ground. voltage to this pin.
ENLDO1 (Pin 3):
Enables the First Low Dropout Linear
LDO1_FB (Pin 9):
Feedback Voltage Input for the First Low Regulator (LDO1) When High. This is a MOS gate input. Dropout Linear Regulator (LDO1). Typically, an external There is an internal 4MΩ pull-down. resistor divider feeds a fraction of the LDO1 output volt- age to this pin.
ENLDO2 (Pin 4):
Enables the Second Low Dropout Linear Regulator (LDO2) When High. This is a MOS gate input.
LDO1 (Pin 10):
Output of the First Low Dropout Linear There is an internal 4MΩ pull-down. Regulator. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
ENBUCK (Pin 5):
Enables the Buck Converter When High. This is a MOS gate input. There is an internal 4MΩ pull-
LDO2 (Pin 11):
Output of the Second Low Dropout Linear down. Regulator. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
BUCKFB (Pin 6):
Feedback Voltage Input for the Buck Regulator. Typically, an external resistor divider feeds a
VIN (Pin 12):
Input Supply. This pin should be bypassed fraction of the buck output voltage to this pin. to ground with a 2.2µF or greater ceramic capacitor.
PGOOD (Pin 7):
Power Good Open-Drain NMOS Output.
Exposed Pad (Pin 13):
Ground. This pin must be soldered The PGOOD pin goes Hi-Z when all enabled outputs are to the PCB. within 8% of final value. Rev A 6 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts
PIN FUNCTIONS SW (Pin 1):
Buck Regulator Switch Node Connection to In-
LDO2_FB (Pin 8):
Feedback Voltage Input for the Second ductor. This pin connects to the drains of the buck regulator’s Low Dropout Linear Regulator (LDO2). Typically, an ex- main PMOS and synchronous NMOS switches. ternal resistor divider feeds a fraction of the LDO2 output
GND (Pin 2):
Ground. voltage to this pin.
ENLDO1 (Pin 3):
Enables the First Low Dropout Linear
LDO1_FB (Pin 9):
Feedback Voltage Input for the First Low Regulator (LDO1) When High. This is a MOS gate input. Dropout Linear Regulator (LDO1). Typically, an external There is an internal 4MΩ pull-down. resistor divider feeds a fraction of the LDO1 output volt- age to this pin.
ENLDO2 (Pin 4):
Enables the Second Low Dropout Linear Regulator (LDO2) When High. This is a MOS gate input.
LDO1 (Pin 10):
Output of the First Low Dropout Linear There is an internal 4MΩ pull-down. Regulator. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
ENBUCK (Pin 5):
Enables the Buck Converter When High. This is a MOS gate input. There is an internal 4MΩ pull-
LDO2 (Pin 11):
Output of the Second Low Dropout Linear down. Regulator. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
BUCKFB (Pin 6):
Feedback Voltage Input for the Buck Regulator. Typically, an external resistor divider feeds a
VIN (Pin 12):
Input Supply. This pin should be bypassed fraction of the buck output voltage to this pin. to ground with a 2.2µF or greater ceramic capacitor.
PGOOD (Pin 7):
Power Good Open-Drain NMOS Output.
Exposed Pad (Pin 13):
Ground. This pin must be soldered The PGOOD pin goes Hi-Z when all enabled outputs are to the PCB. within 8% of final value. Rev A 6 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts
