Datasheet LTC3670 (Analog Devices) - 8

ManufacturerAnalog Devices
DescriptionMonolithic 400mA Buck Regulator with Dual 150mA LDOs in 3mm × 2mm DFN
Pages / Page14 / 8 — OPERATION INTRODUCTION. SYNCHRONOUS BUCK REGULATOR. Burst Mode Operation. …
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OPERATION INTRODUCTION. SYNCHRONOUS BUCK REGULATOR. Burst Mode Operation. Main Control Loop. Soft-Start

OPERATION INTRODUCTION SYNCHRONOUS BUCK REGULATOR Burst Mode Operation Main Control Loop Soft-Start

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LTC3670
OPERATION INTRODUCTION
2.25MHz cycle, or sooner, if the current through it drops The LTC3670 combines a synchronous buck converter to zero before the end of the cycle. with two low dropout linear regulators (LDOs) to provide Through these mechanisms, the error amplifier adjusts the three low voltage outputs from a higher voltage input peak inductor current to deliver the required output power source. The input supply range of 2.5V to 5.5V spans the to regulate the output voltage as sensed by the BUCKFB single-cell Li-Ion operating range. Each output can be pin. All necessary control-loop compensation is internal to independently enabled or shut down via the three enable the step-down switching regulator requiring only a single pins. The output regulation voltages are programmed by ceramic output capacitor for stability. external resistor dividers. At light loads, the inductor current may reach zero before the end of the oscillator cycle, which will turn off the NMOS
SYNCHRONOUS BUCK REGULATOR
synchronous rectifier. In this case, the SW pin goes high The synchronous buck includes many features: It uses a impedance and will show damped “ringing.” This is known Constant-frequency current mode architecture, switching as discontinuous operation and is normal behavior for a at 2.25MHz down to light loads. Automatic Burst Mode switching regulator. operation maintains efficiency in light load and no-load situations. Should the input voltage ever fall below the
Burst Mode Operation
target output voltage, the buck enters 100% duty cycle At light load and no-load conditions, the buck automatically operation. Also known as operating in dropout, this can switches to a power-saving hysteretic control algorithm that extend operating life in battery-powered systems. Soft-start operates the switches intermittently to minimize switching circuitry limits inrush current when powering on. Output losses. Known as Burst Mode operation, the buck cycles current is limited in the event of an output short circuit. The the power switches enough times to charge the output switch node is slew-rate limited to reduce EMI radiation. capacitor to a voltage slightly higher than the regulation The buck regulation control-loop compensation is internal point. The buck then goes into a reduced quiescent current to the IC and requires no external components. sleep mode. In this state, power loss is minimized while the load current is supplied by the output capacitor. Whenever
Main Control Loop
the output voltage drops below a pre-determined value, the An error amplifier monitors the difference between an buck wakes from sleep and cycles the switches again until internal reference voltage and the voltage on the BUCKFB the output capacitor voltage is once again slightly above pin. When the BUCKFB voltage is below the reference, the the regulation point. Sleep time thus depends on load cur- error amplifier output voltage increases. When the BUCKFB rent, because the load current determines the discharge voltage exceeds the reference, the error amplifier output rate of the output capacitor. Should load current increase voltage decreases. above roughly 1/4 of the rated output load current, the buck resumes constant-frequency operation. The error amplifier output controls the peak inductor current through the following mechanism: Paced by a free-running
Soft-Start
2.25MHz oscillator, the main P-channel MOSFET switch is turned on at the start of the oscillator cycle. Current flows Soft-start in the buck regulator is accomplished by gradually from the V increasing the maximum allowed peak inductor current IN supply through this PMOS switch, through the inductor via the SW pin, and into the output capacitor over a 600μs period. This allows the output to rise slowly, and load. When the current reaches the level programmed controlling the inrush current required to charge up the by the output of the error amplifier, the PMOS is shut off, output capacitor. A soft-start cycle occurs whenever the and the N-channel MOSFET synchronous rectifier turns LTC3670 is enabled, or after a fault condition has occurred on. Energy stored in the inductor discharges into the load (thermal shutdown or UVLO). through this NMOS. The NMOS turns off at the end of the Rev A 8 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts
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