Datasheet LTC3410-1.875 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 2.25MHz, 300mA Synchronous Step-Down Regulator in SC70 |
| Pages / Page | 16 / 10 — APPLICATIO S I FOR ATIO. Efficiency Considerations. Figure 2. Power Loss … |
| File Format / Size | PDF / 238 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Efficiency Considerations. Figure 2. Power Loss vs Load Current
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LTC3410-1.875
U U W U APPLICATIO S I FOR ATIO Efficiency Considerations
switched from high to low to high again, a packet of charge, dQ, moves from V The efficiency of a switching regulator is equal to the IN to ground. The resulting dQ/dt is the current out of V output power divided by the input power times 100%. It is IN that is typically larger than the DC bias current. In continuous mode, often useful to analyze individual losses to determine what I is limiting the efficiency and which change would produce GATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom the most improvement. Efficiency can be expressed as: switches. Both the DC bias and gate charge Efficiency = 100% – (L1 + L2 + L3 + ...) losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. where L1, L2, etc. are the individual losses as a percentage of input power. 2. I2R losses are calculated from the resistances of the internal switches, R Although all dissipative elements in the circuit produce SW, and external inductor RL. In continuous mode, the average output current flowing losses, two main sources usually account for most of the through inductor L is “chopped” between the main losses in LTC3410-1.875 circuits: VIN quiescent current switch and the synchronous switch. Thus, the series and I2R losses. The VIN quiescent current loss dominates resistance looking into the SW pin is a function of both the efficiency loss at very low load currents whereas the top and bottom MOSFET RDS(ON) and the duty cycle I2R loss dominates the efficiency loss at medium to high (DC) as follows: load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) actual power lost is of no consequence as illustrated in The RDS(ON) for both the top and bottom MOSFETs can Figure 2. be obtained from the Typical Performance Characteris- 1. The V tics curves. Thus, to obtain I2R losses, simply add R IN quiescent current is due to two components: SW the DC bias current as given in the electrical character- to RL and multiply the result by the square of the average istics and the internal main switch and synchronous output current. switch gate charge currents. The gate charge current Other losses including CIN and COUT ESR dissipative results from switching the gate capacitance of the losses and inductor core losses generally account for less internal power MOSFET switches. Each time the gate is than 2% total additional loss. 1 VIN = 3.6V 0.1 0.01 0.001 POWER LOSS (W) 0.0001 0.00001 0.1 1 10 100 1000 LOAD CURRENT (mA) 34101875 F02
Figure 2. Power Loss vs Load Current
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U U W U APPLICATIO S I FOR ATIO Efficiency Considerations
switched from high to low to high again, a packet of charge, dQ, moves from V The efficiency of a switching regulator is equal to the IN to ground. The resulting dQ/dt is the current out of V output power divided by the input power times 100%. It is IN that is typically larger than the DC bias current. In continuous mode, often useful to analyze individual losses to determine what I is limiting the efficiency and which change would produce GATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom the most improvement. Efficiency can be expressed as: switches. Both the DC bias and gate charge Efficiency = 100% – (L1 + L2 + L3 + ...) losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. where L1, L2, etc. are the individual losses as a percentage of input power. 2. I2R losses are calculated from the resistances of the internal switches, R Although all dissipative elements in the circuit produce SW, and external inductor RL. In continuous mode, the average output current flowing losses, two main sources usually account for most of the through inductor L is “chopped” between the main losses in LTC3410-1.875 circuits: VIN quiescent current switch and the synchronous switch. Thus, the series and I2R losses. The VIN quiescent current loss dominates resistance looking into the SW pin is a function of both the efficiency loss at very low load currents whereas the top and bottom MOSFET RDS(ON) and the duty cycle I2R loss dominates the efficiency loss at medium to high (DC) as follows: load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) actual power lost is of no consequence as illustrated in The RDS(ON) for both the top and bottom MOSFETs can Figure 2. be obtained from the Typical Performance Characteris- 1. The V tics curves. Thus, to obtain I2R losses, simply add R IN quiescent current is due to two components: SW the DC bias current as given in the electrical character- to RL and multiply the result by the square of the average istics and the internal main switch and synchronous output current. switch gate charge currents. The gate charge current Other losses including CIN and COUT ESR dissipative results from switching the gate capacitance of the losses and inductor core losses generally account for less internal power MOSFET switches. Each time the gate is than 2% total additional loss. 1 VIN = 3.6V 0.1 0.01 0.001 POWER LOSS (W) 0.0001 0.00001 0.1 1 10 100 1000 LOAD CURRENT (mA) 34101875 F02
Figure 2. Power Loss vs Load Current
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