Datasheet LTC3548-2 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Dual Synchronous, Fixed/Adjustable Output, 2.25MHz Step-Down DC/DC Regulator |
| Pages / Page | 16 / 3 — ELECTRICAL CHARACTERISTICS The. denotes the specifi cations which apply … |
| File Format / Size | PDF / 418 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS The. denotes the specifi cations which apply over the full operating
Model Line for this Datasheet
Text Version of Document
LTC3548-2
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VMODE Mode Threshold Low 0 0 .5 V Mode Threshold High VIN – 0.5 VIN V POR Power-On Reset Threshold VOUT1, VFB2 Ramping Down, MODE/SYNC = 0V –8.5 % Power-On Reset On-Resistance 100 200 Ω Power-On Reset Delay 262,144 Cycles VRUN RUN Threshold l 0.3 1 1.5 V IRUN RUN Leakage Current l 0.01 1 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
The LTC3548-2 is tested in a proprietary test mode that connects may cause permanent damage to the device. Exposure to any Absolute the output of the error amplifi er to an outside servo loop. Maximum Rating condition for extended periods may affect device
Note 4:
Dynamic supply current is higher due to the internal gate charge reliability and lifetime. being delivered at the switching frequency.
Note 2:
The LTC3548-2 is guaranteed to meet specifi ed performance from
Note 5:
TJ is calculated from the ambient TA and power dissipation PD 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature according to the following formula: TJ = TA + (PD • θJA). range are assured by design, characterization and correlation with
Note 6:
The DFN switch on-resistance is guaranteed by correlation to statistical process controls. wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specifi ed. Burst Mode Operation Pulse-Skipping Mode Load Step
SW SW 5V/DIV 5V/DIV VOUT 200mV/DIV IL I IL L 200mA/DIV 200mA/ 500mA/DIV DIV VOUT I V LOAD OUT 10mV/DIV 500mA/DIV 20mV/DIV 35482 G01 VIN = 3.6V 2μs/DIV 35482 G02 VIN = 3.6V 1μs/DIV 35482 G03 VIN = 3.6V 20μs/DIV VOUT = 1.8V VOUT = 1.8V VOUT = 1.8V ILOAD = 60mA ILOAD = 30mA ILOAD = 80mA TO 800mA CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 35482fb 3
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VMODE Mode Threshold Low 0 0 .5 V Mode Threshold High VIN – 0.5 VIN V POR Power-On Reset Threshold VOUT1, VFB2 Ramping Down, MODE/SYNC = 0V –8.5 % Power-On Reset On-Resistance 100 200 Ω Power-On Reset Delay 262,144 Cycles VRUN RUN Threshold l 0.3 1 1.5 V IRUN RUN Leakage Current l 0.01 1 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
The LTC3548-2 is tested in a proprietary test mode that connects may cause permanent damage to the device. Exposure to any Absolute the output of the error amplifi er to an outside servo loop. Maximum Rating condition for extended periods may affect device
Note 4:
Dynamic supply current is higher due to the internal gate charge reliability and lifetime. being delivered at the switching frequency.
Note 2:
The LTC3548-2 is guaranteed to meet specifi ed performance from
Note 5:
TJ is calculated from the ambient TA and power dissipation PD 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature according to the following formula: TJ = TA + (PD • θJA). range are assured by design, characterization and correlation with
Note 6:
The DFN switch on-resistance is guaranteed by correlation to statistical process controls. wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specifi ed. Burst Mode Operation Pulse-Skipping Mode Load Step
SW SW 5V/DIV 5V/DIV VOUT 200mV/DIV IL I IL L 200mA/DIV 200mA/ 500mA/DIV DIV VOUT I V LOAD OUT 10mV/DIV 500mA/DIV 20mV/DIV 35482 G01 VIN = 3.6V 2μs/DIV 35482 G02 VIN = 3.6V 1μs/DIV 35482 G03 VIN = 3.6V 20μs/DIV VOUT = 1.8V VOUT = 1.8V VOUT = 1.8V ILOAD = 60mA ILOAD = 30mA ILOAD = 80mA TO 800mA CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 35482fb 3
