Datasheet LT1943 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | High Current Quad Output Regulator for TFT LCD Panels |
| Pages / Page | 20 / 10 — OPERATIO. (2a). (2b). Figure 2. LT1943 Power-Up Sequence. (Traces From … |
| File Format / Size | PDF / 278 Kb |
| Document Language | English |
OPERATIO. (2a). (2b). Figure 2. LT1943 Power-Up Sequence. (Traces From Both Photos are Synchronized to the Same Trigger)
Model Line for this Datasheet
Text Version of Document
LT1943
U OPERATIO
The LT1943 is a highly integrated power supply IC con- RUN-SS 2V/DIV taining four separate switching regulators. All four switch- V ing regulators have their own oscillator with frequency LOGIC 5V/DIV foldback and use current mode control. Switching regula- IL1 tor 1 consists of a step-down regulator with a switch 1A/DIV current limit of 2.4A. Switching regulator 2 can be config- SS-234 2V/DIV ured as a step-up or SEPIC converter and has a 2.6A AVDD 20V/DIV switch. Switching regulator 3 consists of a step-up regu- IL2+L3 lator with a 0.35A switch as well as an integrated Schottky 1A/DIV diode. Switching regulator 4 has two feedback pins (FB4 PGOOD 20V/DIV and NFB4) and can directly regulate positive or negative 5ms/DIV 1943 F03a output voltages. The four regulators share common cir-
(2a)
cuitry including input source, voltage reference, and mas- ter oscillator. Operation can be best understood by refer- ring to the Block Diagram as shown in Figure 1. VOFF 10V/DIV If the RUN/SS pin is pulled to ground, the LT1943 is shut I down and draws 35µA from the input source tied to V L4 IN. An 500mA/DIV internal 1.7µA current source charges the external soft- VE3 start capacitor, generating a voltage ramp at this pin. If the 20V/DIV RUN/SS pin exceeds 0.6V, the internal bias circuits turn IL5 on, including the internal regulator, reference, and 1.1MHz 500mA/DIV VCT master oscillator. The master oscillator generates four 2V/DIV clock signals, one for each of the switching regulators. VON Switching regulator 1 will only begin to operate when the 50V/DIV 5ms/DIV 1943 F03b RUN/SS pin reaches 0.8V. Switcher 1 generates VLOGIC, which must be tied to the BIAS pin. When BIAS reaches
(2b)
2.8V, the NPN pulling down on the SS-234 pin turns off, allowing an internal 1.7µA current source to charge the
Figure 2. LT1943 Power-Up Sequence. (Traces From Both Photos are Synchronized to the Same Trigger)
external capacitor tied to the SS-234 pin. When the voltage on the SS-234 pin reaches 0.8V, switchers 2, 3 and 4 are enabled. AV The output is an open collector transistor that is off when DD and VOFF will then begin rising at a ramp rate determined by the capacitor tied to the SS-234 pin. the output is out of regulation, allowing an external resis- When all the outputs reach 90% of their programmed tor to pull the pin high. This pin can be used with a voltages, the NPN pulling down on the C P-channel MOSFET that functions as an output disconnect T pin will turn off, and an internal 20µA current source will charge the exter- for AVDD. nal capacitor tied to the CT pin. When the CT pin reaches The four switchers are current mode regulators. Instead of 1.1V, the output disconnect PNP turns on, connecting directly modulating the duty cycle of the power switch, the VON. In the event of any of the four outputs dropping below feedback loop controls the peak current in the switch 10% of their programmed voltage, PanelProtect circuitry during each cycle. Compared to voltage mode control, pulls the CT pin to GND, disabling VON. current mode control improves loop dynamics and pro- A power good comparator monitors AV vides cycle-by-cycle current limit. DD and turns on when the FB2 pin is at or above 90% of its regulated value. 1943fa 10
U OPERATIO
The LT1943 is a highly integrated power supply IC con- RUN-SS 2V/DIV taining four separate switching regulators. All four switch- V ing regulators have their own oscillator with frequency LOGIC 5V/DIV foldback and use current mode control. Switching regula- IL1 tor 1 consists of a step-down regulator with a switch 1A/DIV current limit of 2.4A. Switching regulator 2 can be config- SS-234 2V/DIV ured as a step-up or SEPIC converter and has a 2.6A AVDD 20V/DIV switch. Switching regulator 3 consists of a step-up regu- IL2+L3 lator with a 0.35A switch as well as an integrated Schottky 1A/DIV diode. Switching regulator 4 has two feedback pins (FB4 PGOOD 20V/DIV and NFB4) and can directly regulate positive or negative 5ms/DIV 1943 F03a output voltages. The four regulators share common cir-
(2a)
cuitry including input source, voltage reference, and mas- ter oscillator. Operation can be best understood by refer- ring to the Block Diagram as shown in Figure 1. VOFF 10V/DIV If the RUN/SS pin is pulled to ground, the LT1943 is shut I down and draws 35µA from the input source tied to V L4 IN. An 500mA/DIV internal 1.7µA current source charges the external soft- VE3 start capacitor, generating a voltage ramp at this pin. If the 20V/DIV RUN/SS pin exceeds 0.6V, the internal bias circuits turn IL5 on, including the internal regulator, reference, and 1.1MHz 500mA/DIV VCT master oscillator. The master oscillator generates four 2V/DIV clock signals, one for each of the switching regulators. VON Switching regulator 1 will only begin to operate when the 50V/DIV 5ms/DIV 1943 F03b RUN/SS pin reaches 0.8V. Switcher 1 generates VLOGIC, which must be tied to the BIAS pin. When BIAS reaches
(2b)
2.8V, the NPN pulling down on the SS-234 pin turns off, allowing an internal 1.7µA current source to charge the
Figure 2. LT1943 Power-Up Sequence. (Traces From Both Photos are Synchronized to the Same Trigger)
external capacitor tied to the SS-234 pin. When the voltage on the SS-234 pin reaches 0.8V, switchers 2, 3 and 4 are enabled. AV The output is an open collector transistor that is off when DD and VOFF will then begin rising at a ramp rate determined by the capacitor tied to the SS-234 pin. the output is out of regulation, allowing an external resis- When all the outputs reach 90% of their programmed tor to pull the pin high. This pin can be used with a voltages, the NPN pulling down on the C P-channel MOSFET that functions as an output disconnect T pin will turn off, and an internal 20µA current source will charge the exter- for AVDD. nal capacitor tied to the CT pin. When the CT pin reaches The four switchers are current mode regulators. Instead of 1.1V, the output disconnect PNP turns on, connecting directly modulating the duty cycle of the power switch, the VON. In the event of any of the four outputs dropping below feedback loop controls the peak current in the switch 10% of their programmed voltage, PanelProtect circuitry during each cycle. Compared to voltage mode control, pulls the CT pin to GND, disabling VON. current mode control improves loop dynamics and pro- A power good comparator monitors AV vides cycle-by-cycle current limit. DD and turns on when the FB2 pin is at or above 90% of its regulated value. 1943fa 10
