Datasheet LTC3406-1.2 (Analog Devices) - 9

LTC3406-1.2
U U W U APPLICATIO S I FOR ATIO
1. The VIN quiescent current is due to two components: To avoid the LTC3406-1.2 from exceeding the maximum the DC bias current as given in the electrical character- junction temperature, the user will need to do some istics and the internal main switch and synchronous thermal analysis. The goal of the thermal analysis is to switch gate charge currents. The gate charge current determine whether the power dissipated exceeds the results from switching the gate capacitance of the maximum junction temperature of the part. The tempera- internal power MOSFET switches. Each time the gate is ture rise is given by: switched from high to low to high again, a packet of TR = (PD)(θJA) charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of V where P IN that is typically larger than D is the power dissipated by the regulator and θJA the DC bias current. In continuous mode, I is the thermal resistance from the junction of the die to the GATECHG = f(Q ambient temperature. T + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and The junction temperature, TJ, is given by: gate charge losses are proportional to VIN and thus T their effects will be more pronounced at higher supply J = TA + TR voltages. where TA is the ambient temperature. 2. I2R losses are calculated from the resistances of the As an example, consider the LTC3406-1.2 with an input internal switches, R voltage of 2.7V, a load current of 600mA and an ambient SW, and external inductor RL. In continuous mode, the average output current flowing temperature of 70°C. From the typical performance graph through inductor L is “chopped” between the main of switch resistance, the RDS(ON) at 70°C is approximately switch and the synchronous switch. Thus, the series 0.52Ω for the P-channel switch and 0.42Ω for the resistance looking into the SW pin is a function of both N-channel switch. Using equation (2) to find the series top and bottom MOSFET R resistance looking into the SW pin gives: DS(ON) and the duty cycle (DC) as follows: RSW = 0.52Ω(0.44) + 0.42Ω(0.56) = 0.46Ω RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) (2) Therefore, power dissipated by the part is: The RDS(ON) for both the top and bottom MOSFETs can P 2 D = ILOAD • RSW = 165.6mW be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add R For the SOT-23 package, the θJA is 250°C/ W. Thus, the SW to R junction temperature of the regulator is: L and multiply the result by the square of the average output current. TJ = 70°C + (0.1656)(250) = 111.4°C Other losses including CIN and COUT ESR dissipative which is below the maximum junction temperature of losses and inductor core losses generally account for less 125°C. than 2% total additional loss. Note that at higher supply voltages, the junction tempera-
Thermal Considerations
ture is lower due to reduced switch resistance (RSW). In most applications the LTC3406-1.2 does not dissipate
Checking Transient Response
much heat due to its high efficiency. But, in applications The regulator loop response can be checked by looking at where the LTC3406-1.2 is running at high ambient tem- the load transient response. Switching regulators take perature with low supply voltage, the heat dissipated may several cycles to respond to a step in load current. When exceed the maximum junction temperature of the part. If a load step occurs, V the junction temperature reaches approximately 150°C, OUT immediately shifts by an amount equal to (∆I both power switches will be turned off and the SW node LOAD • ESR), where ESR is the effective series resistance of C will become high impedance. OUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. 340612fa 9