Datasheet LTC1879 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current |
| Pages / Page | 20 / 6 — PI FU CTIO S. SGND (Pin 1):. PVIN1, PVIN2 (Pins 8, 9):. RUN/SS (Pin 2):. … |
| File Format / Size | PDF / 268 Kb |
| Document Language | English |
PI FU CTIO S. SGND (Pin 1):. PVIN1, PVIN2 (Pins 8, 9):. RUN/SS (Pin 2):. SVIN (Pin 13):. PGOOD (Pin 14):. VFB (Pin 3):. ITH (Pin 4):
Model Line for this Datasheet
Text Version of Document
LTC1879
U U U PI FU CTIO S SGND (Pin 1):
Signal Ground Pin.
PVIN1, PVIN2 (Pins 8, 9):
Power Supply Pins for the Internal Drivers and Switches. These pins should always
RUN/SS (Pin 2):
Combination of Soft-Start and Run be tied together. Control Inputs. Forcing this pin below 0.7V shuts down the device. In shutdown all functions are disabled and device
SVIN (Pin 13):
Signal Power Supply Pin. draws zero supply current. For the proper operation of the
PGOOD (Pin 14):
Power Good Indicator Pin. Power good part, force this pin above 2.5V. Do not leave this pin is an open-drain logic output. The PGOOD pin is pulled to floating. Soft-start can be accomplished by raising the ground when the voltage on the V voltage on this pin gradually with an RC circuit. FB pin is not within ±7.5% of its nominally regulated potential. This pin re-
VFB (Pin 3):
Feedback Pin. Receives the feedback voltage quires a pull-up resistor for power good indication. Power from an external resistor divider across the output. good indication works in all modes of operation.
ITH (Pin 4):
Error Amplifier Compensation Point. The
SYNC/MODE (Pin 15):
External Clock Synchronization current output increases with this control voltage. Nomi- and Mode Select Input. To synchronize, apply an external nal voltage range for this pin is 0.5V to 1.8V. clock with a frequency between 350kHz and 750kHz. To select Burst Mode operation, tie pin to SV
SWP1, SWP2 (Pins 5, 12):
Upper Switch Nodes. These IN. Grounding this pin selects pulse skipping mode. Do not leave this pin pins connect to the drains of the internal main PMOS floating. switches and should always be connected together externally.
PLL_LPF (Pin 16):
Output of the Phase Detector and Control Input of Oscillator. Connect a series RC lowpass
SWN1, SWN2 (Pins 6, 11):
Lower Switch Nodes. These network from this pin to ground if externally synchronized. pins connect to the drains of the internal synchronous If unused, this pin may be left open. NMOS switches and should always be connected together externally.
PGND1, PGND2 (Pins 7, 10):
Power Ground Pins. Ground pins for the internal drivers and switches. These pins should always be tied together. 1879f 6
U U U PI FU CTIO S SGND (Pin 1):
Signal Ground Pin.
PVIN1, PVIN2 (Pins 8, 9):
Power Supply Pins for the Internal Drivers and Switches. These pins should always
RUN/SS (Pin 2):
Combination of Soft-Start and Run be tied together. Control Inputs. Forcing this pin below 0.7V shuts down the device. In shutdown all functions are disabled and device
SVIN (Pin 13):
Signal Power Supply Pin. draws zero supply current. For the proper operation of the
PGOOD (Pin 14):
Power Good Indicator Pin. Power good part, force this pin above 2.5V. Do not leave this pin is an open-drain logic output. The PGOOD pin is pulled to floating. Soft-start can be accomplished by raising the ground when the voltage on the V voltage on this pin gradually with an RC circuit. FB pin is not within ±7.5% of its nominally regulated potential. This pin re-
VFB (Pin 3):
Feedback Pin. Receives the feedback voltage quires a pull-up resistor for power good indication. Power from an external resistor divider across the output. good indication works in all modes of operation.
ITH (Pin 4):
Error Amplifier Compensation Point. The
SYNC/MODE (Pin 15):
External Clock Synchronization current output increases with this control voltage. Nomi- and Mode Select Input. To synchronize, apply an external nal voltage range for this pin is 0.5V to 1.8V. clock with a frequency between 350kHz and 750kHz. To select Burst Mode operation, tie pin to SV
SWP1, SWP2 (Pins 5, 12):
Upper Switch Nodes. These IN. Grounding this pin selects pulse skipping mode. Do not leave this pin pins connect to the drains of the internal main PMOS floating. switches and should always be connected together externally.
PLL_LPF (Pin 16):
Output of the Phase Detector and Control Input of Oscillator. Connect a series RC lowpass
SWN1, SWN2 (Pins 6, 11):
Lower Switch Nodes. These network from this pin to ground if externally synchronized. pins connect to the drains of the internal synchronous If unused, this pin may be left open. NMOS switches and should always be connected together externally.
PGND1, PGND2 (Pins 7, 10):
Power Ground Pins. Ground pins for the internal drivers and switches. These pins should always be tied together. 1879f 6
