Datasheet LTC3861-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing |
| Pages / Page | 38 / 9 — pin FuncTions VCC (Pin 1):. CLKOUT (Pin 12):. FB1 (Pin 2), FB2 (Pin 8):. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
pin FuncTions VCC (Pin 1):. CLKOUT (Pin 12):. FB1 (Pin 2), FB2 (Pin 8):. PHSMD (Pin 13):. COMP1 (Pin 3), COMP2 (Pin 7):
Model Line for this Datasheet
Text Version of Document
LTC3861-1
pin FuncTions VCC (Pin 1):
Chip Supply Voltage. Bypass this pin to GND FREQ pin logic state selects an internal 600kHz or 1MHz with a capacitor (0.1µF to 1µF ceramic) in close proximity preset frequency. to the chip.
CLKOUT (Pin 12):
Digital Output Used for Daisychain-
FB1 (Pin 2), FB2 (Pin 8):
Error Amplifier Inverting Input. ing Multiple LTC3861-1 ICs in Multiphase Systems. The FB1 or FB2 can be connected to VSNSOUT via a resistor PHSMD pin voltage controls the relationship between divider for remote VOUT sensing. The bottom of the divider CH1 and CH2 as well as between CH1 and CLKOUT. When should be connected to the SGND pin of the IC. The other both RUN pins are driven low, the CLKOUT pin is actively FB, when used, is typically connected to the second VOUT pulled up to VCC. via a resistor divider, also terminated at the IC SGND pin.
PHSMD (Pin 13):
Phase Mode Pin. The PHSMD pin volt-
COMP1 (Pin 3), COMP2 (Pin 7):
Error Amplifier Outputs. age programs the phase relationship between CH1 and PWM duty cycle increases with this control voltage. The CH2 rising PWM signals, as well as the phase relationship error amplifiers in the LTC3861-1 are true operational between CH1 PWM signal and CLKOUT. Floating this pin amplifiers with low output impedance. As a result, the or connecting it to either VCC or SGND changes the phase outputs of two active error amplifiers cannot be directly relationship between CH1, CH2 and CLKOUT. connected together! For multiphase operation, connecting
ISNS1N (Pin 21), ISNS2N (Pin 20):
Current Sense Am- the FB pin on an error amplifier to VCC will three-state the plifier (–) Input. The (–) input to the current amplifier is output of that amplifier. Multiphase operation can then be normally connected to the respective V achieved by connecting all of the COMP pins together and OUT at the inductor. using one channel as the master and all others as slaves.
ISNS1P (Pin 22), ISNS2P (Pin 19):
Current Sense Ampli- When the RUN pin is low, the respective COMP pin is fier (+) Input. The (+) input to the current sense amplifier actively pulled down to ground. is normally connected to the midpoint of the inductor’s parallel RC sense circuit or to the node between the induc-
VSNSOUT (Pin 4):
Differential Amplifier Output. Connect tor and sense resistor if using a discrete sense resistor. to FB1 or FB2 with a resistive divider and compensation network for remote VOUT sensing.
ILIM1 (Pin 23), ILIM2 (Pin 18):
Current Comparator Sense Voltage Limit Selection Pin. Connect a resistor from this
VSNSN (Pin 5):
Differential Sense Amplifier Inverting Input. pin to SGND. This pin sources 20µA. The resultant voltage Connect this pin to sense ground at the output load. sets the threshold for overcurrent protection.
VSNSP (Pin 6):
Differential Sense Amplifier Noninverting
RUN1 (Pin 24), RUN2 (Pin 17):
Run Control Inputs. A Input. Connect this pin to VOUT at the output load. voltage above 2.25V on either pin turns on the IC. How-
FREQ (Pin 10):
Frequency Set/Select Pin. This pin sources ever, forcing either of these pins below 2V causes the 20µA current. If CLKIN is high or floating, then a resistor IC to shut down that particular channel. There are 1.5µA between this pin and SGND sets the switching frequency. If pull-up currents for these pins. CLKIN is low, the logic state of this pin selects an internal
PWM1 (Pin 25), PWM2 (Pin 16):
(Top) Gate Signal Out- 600kHz or 1MHz preset frequency. put. This signal goes to the PWM or top gate input of the
CLKIN (Pin 11):
External Clock Synchronization Input. external gate driver or integrated driver MOSFET. This is Applying an external clock between 250kHz to 2.25MHz a three-state compatible output. will cause the switching frequency to synchronize to the
PWMEN1 (Pin 26), PWMEN2 (Pin 15):
Enable Pin for clock. CLKIN is pulled high to VCC by a 50k internal resis- Non-Three-State compatible drivers. This pin has an in- tor. The rising edge of the CLKIN input waveform will align ternal open-drain pull-up to V with the rising edge of PWM1 in closed-loop operation. If CC. An external resistor to SGND is required. This pin is low when the corresponding CLKIN is high or floating, a resistor from the FREQ pin to PWM pin is high impedance. SGND sets the switching frequency. If CLKIN is low, the 38611fb For more information www.linear.com/LTC3861-1 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Related Parts
pin FuncTions VCC (Pin 1):
Chip Supply Voltage. Bypass this pin to GND FREQ pin logic state selects an internal 600kHz or 1MHz with a capacitor (0.1µF to 1µF ceramic) in close proximity preset frequency. to the chip.
CLKOUT (Pin 12):
Digital Output Used for Daisychain-
FB1 (Pin 2), FB2 (Pin 8):
Error Amplifier Inverting Input. ing Multiple LTC3861-1 ICs in Multiphase Systems. The FB1 or FB2 can be connected to VSNSOUT via a resistor PHSMD pin voltage controls the relationship between divider for remote VOUT sensing. The bottom of the divider CH1 and CH2 as well as between CH1 and CLKOUT. When should be connected to the SGND pin of the IC. The other both RUN pins are driven low, the CLKOUT pin is actively FB, when used, is typically connected to the second VOUT pulled up to VCC. via a resistor divider, also terminated at the IC SGND pin.
PHSMD (Pin 13):
Phase Mode Pin. The PHSMD pin volt-
COMP1 (Pin 3), COMP2 (Pin 7):
Error Amplifier Outputs. age programs the phase relationship between CH1 and PWM duty cycle increases with this control voltage. The CH2 rising PWM signals, as well as the phase relationship error amplifiers in the LTC3861-1 are true operational between CH1 PWM signal and CLKOUT. Floating this pin amplifiers with low output impedance. As a result, the or connecting it to either VCC or SGND changes the phase outputs of two active error amplifiers cannot be directly relationship between CH1, CH2 and CLKOUT. connected together! For multiphase operation, connecting
ISNS1N (Pin 21), ISNS2N (Pin 20):
Current Sense Am- the FB pin on an error amplifier to VCC will three-state the plifier (–) Input. The (–) input to the current amplifier is output of that amplifier. Multiphase operation can then be normally connected to the respective V achieved by connecting all of the COMP pins together and OUT at the inductor. using one channel as the master and all others as slaves.
ISNS1P (Pin 22), ISNS2P (Pin 19):
Current Sense Ampli- When the RUN pin is low, the respective COMP pin is fier (+) Input. The (+) input to the current sense amplifier actively pulled down to ground. is normally connected to the midpoint of the inductor’s parallel RC sense circuit or to the node between the induc-
VSNSOUT (Pin 4):
Differential Amplifier Output. Connect tor and sense resistor if using a discrete sense resistor. to FB1 or FB2 with a resistive divider and compensation network for remote VOUT sensing.
ILIM1 (Pin 23), ILIM2 (Pin 18):
Current Comparator Sense Voltage Limit Selection Pin. Connect a resistor from this
VSNSN (Pin 5):
Differential Sense Amplifier Inverting Input. pin to SGND. This pin sources 20µA. The resultant voltage Connect this pin to sense ground at the output load. sets the threshold for overcurrent protection.
VSNSP (Pin 6):
Differential Sense Amplifier Noninverting
RUN1 (Pin 24), RUN2 (Pin 17):
Run Control Inputs. A Input. Connect this pin to VOUT at the output load. voltage above 2.25V on either pin turns on the IC. How-
FREQ (Pin 10):
Frequency Set/Select Pin. This pin sources ever, forcing either of these pins below 2V causes the 20µA current. If CLKIN is high or floating, then a resistor IC to shut down that particular channel. There are 1.5µA between this pin and SGND sets the switching frequency. If pull-up currents for these pins. CLKIN is low, the logic state of this pin selects an internal
PWM1 (Pin 25), PWM2 (Pin 16):
(Top) Gate Signal Out- 600kHz or 1MHz preset frequency. put. This signal goes to the PWM or top gate input of the
CLKIN (Pin 11):
External Clock Synchronization Input. external gate driver or integrated driver MOSFET. This is Applying an external clock between 250kHz to 2.25MHz a three-state compatible output. will cause the switching frequency to synchronize to the
PWMEN1 (Pin 26), PWMEN2 (Pin 15):
Enable Pin for clock. CLKIN is pulled high to VCC by a 50k internal resis- Non-Three-State compatible drivers. This pin has an in- tor. The rising edge of the CLKIN input waveform will align ternal open-drain pull-up to V with the rising edge of PWM1 in closed-loop operation. If CC. An external resistor to SGND is required. This pin is low when the corresponding CLKIN is high or floating, a resistor from the FREQ pin to PWM pin is high impedance. SGND sets the switching frequency. If CLKIN is low, the 38611fb For more information www.linear.com/LTC3861-1 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Related Parts
