Datasheet LTC3860 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Current Sharing |
| Pages / Page | 36 / 10 — OPERATION (Refer to Functional Diagram). Main Control Architecture. … |
| File Format / Size | PDF / 451 Kb |
| Document Language | English |
OPERATION (Refer to Functional Diagram). Main Control Architecture. Current Sharing. When multiple ICs are
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LTC3860
OPERATION (Refer to Functional Diagram) Main Control Architecture
on-time of approximately 20ns and a minimum off-time of approximately 1/12th the switching period. The LTC3860 is a dual-channel/dual-phase, constant frequency, voltage mode controller for DC/DC step-down
Current Sharing
applications. It is designed to be used in a synchronous switching architecture with external integrated-driver In multiphase operation, the LTC3860 also incorporates an MOSFETs or external drivers and N-channel MOSFETs auxiliary current sharing loop. Inductor current is sampled using single wire three-state PWM interfaces. The each cycle. The master’s current sense amplifi er output controller allows the use of sense resistors or lossless is averaged at the IAVG pin. A small capacitor connected inductor DCR current sensing to maintain current balance from IAVG to GND (typically 100pF) stores a voltage cor- between phases and to provide overcurrent protection. responding to the instantaneous average current of the The operating frequency is selectable from 250kHz to master. Each phase integrates the difference between its 1.25MHz. To multiply the effective switching frequency, current and the master’s. Within each phase the integrator multiphase operation can be extended to 3, 4, 6, or 12 output is proportionally summed with the system error phases by paralleling up to 6 controllers. In single or 3- amplifi er voltage (COMP), adjusting that phase’s duty phase operation, the 2nd or 4th channel can be used as cycle to equalize the currents.
When multiple ICs are
an independent output.
daisychained the IAVG pins must be connected together
.
When the phases are operated independently, the I
The output of the differential amplifi er is connected to
AVG pin should be tied to ground.
Figure 1 shows a transient the error amplifi er inverting input (FB) through a resistor load step with 50% inductor mismatch in a 2-phase system. divider. The remote sense differential amplifi er output (VSNSOUT) provides a signal equal to the differential voltage (V VOUT(AC) SNSP – VSNSN) sensed across the output capacitor, but 100mV/DIV re-referenced to the local ground (SGND). This permits ILOAD accurate voltage sensing at the load, without regard to 20A/DIV the potential difference between its ground and local IL1 = 320nH 10A/DIV ground. IL2 = 220nH 10A/DIV In the main voltage mode control loop, the error ampli- 3860 F01 V 50μs/DIV IN = 12V fi er output (COMP) directly controls the converter duty VOUT = 1.2V ILOAD = 0A TO 25A cycle in order to drive the FB pin to 0.6V in steady state. Dynamic changes in output load current can perturb the
Figure 1
output voltage. When the output is below regulation, COMP rises, increasing the duty cycle. If the output rises above regulation, COMP will decrease, decreasing the
Overcurrent Protection
duty cycle. As the output approaches regulation, COMP The current sense amplifi er outputs also connect to will settle to the steady-state value representing the step- overcurrent (OC) comparators that provide fault protec- down conversion ratio. tion in the case of an output short. When an OC fault is In normal operation, the PWM latch is set high at the begin- detected, the controller three-states the PWM output, ning of the clock cycle (assuming COMP > 0.5V). When resets the soft-start capacitor, and waits for 32768 clock the (line feedforward compensated) PWM ramp exceeds cycles before attempting to start up again. The LTC3860 the COMP voltage, the comparator trips and resets the also provides negative OC (NOC) protection by preventing PWM latch. If COMP is less than 0.5V at the beginning turn-on of the bottom MOSFET during a negative OC fault of the clock cycle, as in the case of an overvoltage at the condition. The negative OC threshold is equal to –3/4 the outputs, the PWM pin remains low throughout the entire positive OC threshold. See Applications Information for cycle. When the PWM pin goes high it has a minimum guidelines on setting these thresholds. 3860fc 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
OPERATION (Refer to Functional Diagram) Main Control Architecture
on-time of approximately 20ns and a minimum off-time of approximately 1/12th the switching period. The LTC3860 is a dual-channel/dual-phase, constant frequency, voltage mode controller for DC/DC step-down
Current Sharing
applications. It is designed to be used in a synchronous switching architecture with external integrated-driver In multiphase operation, the LTC3860 also incorporates an MOSFETs or external drivers and N-channel MOSFETs auxiliary current sharing loop. Inductor current is sampled using single wire three-state PWM interfaces. The each cycle. The master’s current sense amplifi er output controller allows the use of sense resistors or lossless is averaged at the IAVG pin. A small capacitor connected inductor DCR current sensing to maintain current balance from IAVG to GND (typically 100pF) stores a voltage cor- between phases and to provide overcurrent protection. responding to the instantaneous average current of the The operating frequency is selectable from 250kHz to master. Each phase integrates the difference between its 1.25MHz. To multiply the effective switching frequency, current and the master’s. Within each phase the integrator multiphase operation can be extended to 3, 4, 6, or 12 output is proportionally summed with the system error phases by paralleling up to 6 controllers. In single or 3- amplifi er voltage (COMP), adjusting that phase’s duty phase operation, the 2nd or 4th channel can be used as cycle to equalize the currents.
When multiple ICs are
an independent output.
daisychained the IAVG pins must be connected together
.
When the phases are operated independently, the I
The output of the differential amplifi er is connected to
AVG pin should be tied to ground.
Figure 1 shows a transient the error amplifi er inverting input (FB) through a resistor load step with 50% inductor mismatch in a 2-phase system. divider. The remote sense differential amplifi er output (VSNSOUT) provides a signal equal to the differential voltage (V VOUT(AC) SNSP – VSNSN) sensed across the output capacitor, but 100mV/DIV re-referenced to the local ground (SGND). This permits ILOAD accurate voltage sensing at the load, without regard to 20A/DIV the potential difference between its ground and local IL1 = 320nH 10A/DIV ground. IL2 = 220nH 10A/DIV In the main voltage mode control loop, the error ampli- 3860 F01 V 50μs/DIV IN = 12V fi er output (COMP) directly controls the converter duty VOUT = 1.2V ILOAD = 0A TO 25A cycle in order to drive the FB pin to 0.6V in steady state. Dynamic changes in output load current can perturb the
Figure 1
output voltage. When the output is below regulation, COMP rises, increasing the duty cycle. If the output rises above regulation, COMP will decrease, decreasing the
Overcurrent Protection
duty cycle. As the output approaches regulation, COMP The current sense amplifi er outputs also connect to will settle to the steady-state value representing the step- overcurrent (OC) comparators that provide fault protec- down conversion ratio. tion in the case of an output short. When an OC fault is In normal operation, the PWM latch is set high at the begin- detected, the controller three-states the PWM output, ning of the clock cycle (assuming COMP > 0.5V). When resets the soft-start capacitor, and waits for 32768 clock the (line feedforward compensated) PWM ramp exceeds cycles before attempting to start up again. The LTC3860 the COMP voltage, the comparator trips and resets the also provides negative OC (NOC) protection by preventing PWM latch. If COMP is less than 0.5V at the beginning turn-on of the bottom MOSFET during a negative OC fault of the clock cycle, as in the case of an overvoltage at the condition. The negative OC threshold is equal to –3/4 the outputs, the PWM pin remains low throughout the entire positive OC threshold. See Applications Information for cycle. When the PWM pin goes high it has a minimum guidelines on setting these thresholds. 3860fc 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
