Datasheet ADP1829 (Analog Devices) - 5

Data Sheet ADP1829 ABSOLUTE MAXIMUM RATINGS Table 2.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a IN, EN1, EN2 −0.3 V to +20.5 V stress rating only; functional operation of the product at these BST1, BST2 −0.3 V to +30 V or any other conditions above those indicated in the operational BST1, BST2 to SW1, SW2 −0.3 V to +6 V section of this specification is not implied. Operation beyond CSL1, CSL2 −1 V to +30 V the maximum operating conditions for extended periods may SW1, SW2 −2 V to +30 V affect product reliability. DH1 SW1 − 0.3 V to BST1 + 0.3 V DH2 SW2 − 0.3 V to BST2 + 0.3 V
ESD CAUTION
DL1, DL2 to PGND

−0.3 V to PV + 0.3 V PGND to GND ±2 V LDOSD, SYNC, FREQ, COMP1, −0.3 V to +6 V COMP2, SS1, SS2, FB1, FB2, VREG, PV, POK1, POK2, TRK1, TRK2 θJA 4-Layer 45°C/W (JEDEC Standard Board)1, 2 Operating Ambient Temperature −40°C < TA< +85°C Operating Junction Temperature3 −40°C < TJ < +125°C Storage Temperature −65°C to +150°C 1 Measured with exposed pad attached to PCB. 2 Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is application and board-layout dependent. In applica- tions where high maximum power dissipation exists, attention to thermal dissipation issues in board design is required. For more information, refer to Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 3 In applications where high power dissipation and poor package thermal resistance are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA_MAX) is dependent on the maximum operating junction temperature (TJ_MAX_OP = 125oC), the maximum power dissipation of the device in the application (PD_MAX), and the junction- to-ambient thermal resistance of the part/package in the application (θJA) and is given by the following equation: TA_MAX = TJ_MAX_OP – (θJA × PD_MAX). Rev. D | Page 5 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT POWER START-UP LOGIC INTERNAL LINEAR REGULATOR OSCILLATOR AND SYNCHRONIZATION ERROR AMPLIFIER SOFT START POWER OK INDICATOR TRACKING MOSFET DRIVERS CURRENT LIMIT APPLICATIONS INFORMATION SELECTING THE INPUT CAPACITOR Selecting the Output LC Filter SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SOFT START VOLTAGE TRACKING COINCIDENT TRACKING RATIOMETRIC TRACKING Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES LFCSP PACKAGE CONSIDERATIONS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE