Datasheet LTC3827-1 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Low IQ, Dual, 2-Phase Synchronous Step-Down Controller |
| Pages / Page | 32 / 8 — PIN FUNCTIONS. ITH1, ITH2 (Pins 1, 13):. EXTVCC (Pin 20):. FB1, VFB2 … |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
PIN FUNCTIONS. ITH1, ITH2 (Pins 1, 13):. EXTVCC (Pin 20):. FB1, VFB2 (Pins 2, 12):. PGND (Pin 21):
Model Line for this Datasheet
Text Version of Document
LTC3827-1
PIN FUNCTIONS ITH1, ITH2 (Pins 1, 13):
Error Amplifi er Outputs and Switch-
EXTVCC (Pin 20):
External Power Input to an Internal LDO ing Regulator Compensation Points. Each associa-ted Connected to INTVCC. This LDO supplies INTVCC power, channel’s current comparator trip point increases with bypassing the internal LDO powered from VIN whenever this control voltage. EXTVCC is higher than 4.7V. See EXTVCC Connection in
V
the Applications Information section. Do not exceed 10V
FB1, VFB2 (Pins 2, 12):
Receives the remotely sensed feedback voltage for each controller from an external on this pin. resistive divider across the output.
PGND (Pin 21):
Driver Power Ground. Connects to the sources
SENSE1+, SENSE2+ (Pins 3, 11):
The (+) Input to the of bottom (synchronous) N-channel MOSFETs, anodes of Differential Current Comparators. The I the Schottky rectifi ers and the (–) terminal(s) of CIN. TH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in
VIN (Pin 22):
Main Supply Pin. A bypass capacitor should conjunction with RSENSE set the current trip threshold. be tied between this pin and the signal ground pin.
SENSE1–, SENSE2– (Pins 4, 10):
The (–) Input to the
BG1, BG2 (Pins 23, 18):
High Current Gate Drives for Bot- Differential Current Comparators. tom (Synchronous) N-Channel MOSFETs. Voltage swing
PLLLPF (Pin 5):
The phase-locked loop’s lowpass fi lter is at these pins is from ground to INTVCC. tied to this pin when synchronizing to an external clock.
BOOST1, BOOST2 (Pins 24, 17):
Bootstrapped Supplies Alternatively, tie this pin to GND, INTVCC or leave fl oating to to the Topside Floating Drivers. Capacitors are connected select 250kHz, 530kHz or 400kHz switching frequency. between the BOOST and SW pins and Schottky diodes are
PLLIN/MODE (Pin 6):
External Synchronization Input to tied between the BOOST and INTVCC pins. Voltage swing Phase Detector and Forced Continuous Control Input. When at the BOOST pins is from INTVCC to (VIN + INTVCC). an external clock is applied to this pin, the phase-locked
SW1, SW2 (Pins 25, 16):
Switch Node Connections to loop will force the rising TG1 signal to be synchronized Inductors. Voltage swing at these pins is from a Schottky with the rising edge of the external clock. In this case, an diode (external) voltage drop below ground to VIN. R-C fi lter must be connected to the PLLLPF pin. When
TG1, TG2 (Pins 26, 15):
High Current Gate Drives for Top not synchronizing to an external clock, this input, which N-Channel MOSFETs. These are the outputs of fl oating acts on both controllers, determines how the LTC3827-1 drivers with a voltage swing equal to INTV operates at light loads. Pulling this pin below 0.7V selects CC – 0.5V su- perimposed on the switch node voltage SW. Burst Mode operation. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to
PGOOD1 (Pin 27):
Open-Drain Logic Output. PGOOD1 is a voltage greater than 0.9V and less than INTVCC –1.2V pulled to ground when the voltage on the VFB1 pin is not selects pulse-skipping operation. within ±10% of its set point.
SGND (Pin 7):
Small-Signal Ground common to both
TRACK/SS1, TRACK/SS2 (Pins 28, 14):
External Track- controllers, must be routed separately from high cur- ing and Soft-Start Input. The LTC3827-1 regulates the rent grounds to the common (–) terminals of the VFB1,2 voltage to the smaller of 0.8V or the voltage on the CIN capacitors. TRACK/SS1,2 pin. A internal 1μA pull-up current source is connected to this pin. A capacitor to ground at this
RUN1, RUN2 (Pins 8, 9):
Digital Run Control Inputs for pin sets the ramp time to fi nal regulated output voltage. Each Controller. Forcing either of these pins below 0.7V Alternatively, a resistor divider on another voltage supply shuts down that controller. Forcing both of these pins connected to this pin allows the LTC3827-1 output to track below 0.7V shuts down the entire LTC3827-1, reducing the other supply during startup. quiescent current to approximately 8μA.
INTVCC (Pin 19):
Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7μF tantalum or other low ESR capacitor. 38271fe 8
PIN FUNCTIONS ITH1, ITH2 (Pins 1, 13):
Error Amplifi er Outputs and Switch-
EXTVCC (Pin 20):
External Power Input to an Internal LDO ing Regulator Compensation Points. Each associa-ted Connected to INTVCC. This LDO supplies INTVCC power, channel’s current comparator trip point increases with bypassing the internal LDO powered from VIN whenever this control voltage. EXTVCC is higher than 4.7V. See EXTVCC Connection in
V
the Applications Information section. Do not exceed 10V
FB1, VFB2 (Pins 2, 12):
Receives the remotely sensed feedback voltage for each controller from an external on this pin. resistive divider across the output.
PGND (Pin 21):
Driver Power Ground. Connects to the sources
SENSE1+, SENSE2+ (Pins 3, 11):
The (+) Input to the of bottom (synchronous) N-channel MOSFETs, anodes of Differential Current Comparators. The I the Schottky rectifi ers and the (–) terminal(s) of CIN. TH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in
VIN (Pin 22):
Main Supply Pin. A bypass capacitor should conjunction with RSENSE set the current trip threshold. be tied between this pin and the signal ground pin.
SENSE1–, SENSE2– (Pins 4, 10):
The (–) Input to the
BG1, BG2 (Pins 23, 18):
High Current Gate Drives for Bot- Differential Current Comparators. tom (Synchronous) N-Channel MOSFETs. Voltage swing
PLLLPF (Pin 5):
The phase-locked loop’s lowpass fi lter is at these pins is from ground to INTVCC. tied to this pin when synchronizing to an external clock.
BOOST1, BOOST2 (Pins 24, 17):
Bootstrapped Supplies Alternatively, tie this pin to GND, INTVCC or leave fl oating to to the Topside Floating Drivers. Capacitors are connected select 250kHz, 530kHz or 400kHz switching frequency. between the BOOST and SW pins and Schottky diodes are
PLLIN/MODE (Pin 6):
External Synchronization Input to tied between the BOOST and INTVCC pins. Voltage swing Phase Detector and Forced Continuous Control Input. When at the BOOST pins is from INTVCC to (VIN + INTVCC). an external clock is applied to this pin, the phase-locked
SW1, SW2 (Pins 25, 16):
Switch Node Connections to loop will force the rising TG1 signal to be synchronized Inductors. Voltage swing at these pins is from a Schottky with the rising edge of the external clock. In this case, an diode (external) voltage drop below ground to VIN. R-C fi lter must be connected to the PLLLPF pin. When
TG1, TG2 (Pins 26, 15):
High Current Gate Drives for Top not synchronizing to an external clock, this input, which N-Channel MOSFETs. These are the outputs of fl oating acts on both controllers, determines how the LTC3827-1 drivers with a voltage swing equal to INTV operates at light loads. Pulling this pin below 0.7V selects CC – 0.5V su- perimposed on the switch node voltage SW. Burst Mode operation. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to
PGOOD1 (Pin 27):
Open-Drain Logic Output. PGOOD1 is a voltage greater than 0.9V and less than INTVCC –1.2V pulled to ground when the voltage on the VFB1 pin is not selects pulse-skipping operation. within ±10% of its set point.
SGND (Pin 7):
Small-Signal Ground common to both
TRACK/SS1, TRACK/SS2 (Pins 28, 14):
External Track- controllers, must be routed separately from high cur- ing and Soft-Start Input. The LTC3827-1 regulates the rent grounds to the common (–) terminals of the VFB1,2 voltage to the smaller of 0.8V or the voltage on the CIN capacitors. TRACK/SS1,2 pin. A internal 1μA pull-up current source is connected to this pin. A capacitor to ground at this
RUN1, RUN2 (Pins 8, 9):
Digital Run Control Inputs for pin sets the ramp time to fi nal regulated output voltage. Each Controller. Forcing either of these pins below 0.7V Alternatively, a resistor divider on another voltage supply shuts down that controller. Forcing both of these pins connected to this pin allows the LTC3827-1 output to track below 0.7V shuts down the entire LTC3827-1, reducing the other supply during startup. quiescent current to approximately 8μA.
INTVCC (Pin 19):
Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7μF tantalum or other low ESR capacitor. 38271fe 8
