Datasheet LTC3737 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual 2-Phase, No RSENSE DC/DC Controller with Output Tracking |
| Pages / Page | 24 / 10 — OPERATIO. (Refer to Functional Diagram). Peak Current Sense Voltage … |
| File Format / Size | PDF / 282 Kb |
| Document Language | English |
OPERATIO. (Refer to Functional Diagram). Peak Current Sense Voltage Selection and Slope. Compensation (IPRG1 and IPRG2 Pins)
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LTC3737
U OPERATIO (Refer to Functional Diagram) Peak Current Sense Voltage Selection and Slope
The peak inductor current is determined by the peak sense
Compensation (IPRG1 and IPRG2 Pins)
voltage and the on-resistance of the external P-channel MOSFET: When a controller is operating below 20% duty cycle, the peak current sense voltage (between the SENSE+ and SW ∆V pins) allowed across the external P-channel MOSFET is SENSE MAX ( ) IPK = determined by: RDS ON ( ) A(V – . 0 7V ITH )
Power Good (PGOOD) Pin
∆VSENSE MAX ( ) = 10 A window comparator monitors both feedback voltages where A is a constant determined by the state of the IPRG and the open-drain PGOOD output pin is pulled low when pins. either or both feedback voltages are not within ±10% of the 0.6V reference voltage. PGOOD is low when the Floating the IPRG pin selects A = 1; tying IPRG to VIN LTC3737 is shutdown or in undervoltage lockout. selects A = 5/3; tying IPRG to SGND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the
2-Phase Operation
maximum sense voltage allowed across the external Why the need for 2-phase operation? Until recently, con- P-channel MOSFET is 125mV, 85mV or 204mV for the stant frequency dual switching regulators operated both three respective states of the IPRG pin. The peak sense controllers in phase (i.e., single phase operation). This voltages for the two controllers can be independently means that both topside MOSFETs (P-channel) are turned selected by the IPRG1 and IPRG2 pins. on at the same time, causing current pulses of up to twice However, once the controller’s duty cycle exceeds 20%, the amplitude of those from a single regulator to be drawn slope compensation begins and effectively reduces the from the input capacitor. These large amplitude pulses peak sense voltage by a scale factor given by the curve in increase the total RMS current flowing in the input capaci- Figure 2. tor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the 110 input capacitor and input power supply. 100 90 With 2-phase operation, the two controllers of the LTC3737 80 are operated 180 degrees out of phase. This effectively 70 interleaves the current pulses coming from the topside (%) 60 MAX MOSFET switches, greatly reducing the time where they 50 overlap and add together. The result is a significant SF = I/I 40 reduction in the total RMS current, which in turn allows the 30 20 use of smaller, less expensive input capacitors, reduces 10 shielding requirements for EMI and improves real world 0 operating efficiency. 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) Figure 3 shows qualitatively example waveforms for a 3737 F02 single phase dual controller versus a 2-phase LTC3737
Figure 2. Maximum Peak Current vs Duty Cycle
system. In this case, 2.5V and 1.8V outputs, each drawing 3737fa 10
U OPERATIO (Refer to Functional Diagram) Peak Current Sense Voltage Selection and Slope
The peak inductor current is determined by the peak sense
Compensation (IPRG1 and IPRG2 Pins)
voltage and the on-resistance of the external P-channel MOSFET: When a controller is operating below 20% duty cycle, the peak current sense voltage (between the SENSE+ and SW ∆V pins) allowed across the external P-channel MOSFET is SENSE MAX ( ) IPK = determined by: RDS ON ( ) A(V – . 0 7V ITH )
Power Good (PGOOD) Pin
∆VSENSE MAX ( ) = 10 A window comparator monitors both feedback voltages where A is a constant determined by the state of the IPRG and the open-drain PGOOD output pin is pulled low when pins. either or both feedback voltages are not within ±10% of the 0.6V reference voltage. PGOOD is low when the Floating the IPRG pin selects A = 1; tying IPRG to VIN LTC3737 is shutdown or in undervoltage lockout. selects A = 5/3; tying IPRG to SGND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the
2-Phase Operation
maximum sense voltage allowed across the external Why the need for 2-phase operation? Until recently, con- P-channel MOSFET is 125mV, 85mV or 204mV for the stant frequency dual switching regulators operated both three respective states of the IPRG pin. The peak sense controllers in phase (i.e., single phase operation). This voltages for the two controllers can be independently means that both topside MOSFETs (P-channel) are turned selected by the IPRG1 and IPRG2 pins. on at the same time, causing current pulses of up to twice However, once the controller’s duty cycle exceeds 20%, the amplitude of those from a single regulator to be drawn slope compensation begins and effectively reduces the from the input capacitor. These large amplitude pulses peak sense voltage by a scale factor given by the curve in increase the total RMS current flowing in the input capaci- Figure 2. tor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the 110 input capacitor and input power supply. 100 90 With 2-phase operation, the two controllers of the LTC3737 80 are operated 180 degrees out of phase. This effectively 70 interleaves the current pulses coming from the topside (%) 60 MAX MOSFET switches, greatly reducing the time where they 50 overlap and add together. The result is a significant SF = I/I 40 reduction in the total RMS current, which in turn allows the 30 20 use of smaller, less expensive input capacitors, reduces 10 shielding requirements for EMI and improves real world 0 operating efficiency. 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) Figure 3 shows qualitatively example waveforms for a 3737 F02 single phase dual controller versus a 2-phase LTC3737
Figure 2. Maximum Peak Current vs Duty Cycle
system. In this case, 2.5V and 1.8V outputs, each drawing 3737fa 10
