Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices)

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Blackfin Embedded Processor ADSP-BF539/ ADSP-BF539F FEATURES External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Up to 533 MHz high performance Blackfin processor Flexible memory booting options from SPI and external Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, memory 40-bit shifter RISC-like register and instruction model for ease of PERIPHERALS programming and compiler friendly support Parallel peripheral interface (PPI), supporting ITU-R 656 Advanced debug, trace, and performance monitoring video data formats Wide range of operating voltages; see Operating Conditions 4 dual-channel, full-duplex synchronous serial ports, on Page 26 supporting 16 stereo I2S channels Qualified for automotive applications 2 DMA controllers supporting 26 peripheral DMAs Programmable on-chip voltage regulator 4 memory-to-memory DMAs 316-ball Pb-free CSP_BGA package Controller area network (CAN) 2.0B controller MEMORY Media transceiver (MXVR) for connection to a MOST network 148K bytes of on-chip memory 3 SPI-compatible ports 16K bytes of instruction SRAM/cache Three 32-bit timer/counters with PWM support 64K bytes of instruction SRAM 3 UARTs with support for IrDA 32K bytes of data SRAM 2 TWI controllers compatible with I2C industry standard 32K bytes of data SRAM/cache Up to 38 general-purpose I/O pins (GPIO) 4K bytes of scratchpad SRAM Up to 16 general-purpose flag pins (GPF) Optional 8M bit parallel flash with boot option Real-time clock, watchdog timer, and 32-bit core timer Memory management unit providing memory protection On-chip PLL capable of frequency multiplication Debug/JTAG interface VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS S U B S TWI0-1 INTERRUPT ES C WATCHDOG
B
CONTROLLER C TIMER LA CAN 2.0B GPIO RA PORT E DMA CORE H RTC C BUS 2 IP MXVR R E P PPI DMA L1 INSTRUCTION L1 DATA DMA SPI1-2 GPIO CONTROLLER1 MEMORY MEMORY CONTROLLER 0 GPIO 0 PORT 1 S TIMER0-2 PORT D S UART1-2 BU F DMA BU S DMA CORE DMA EXTERNAL S S BUS 1 E SPI0 S EXTERNAL DMA CORE BUS 0 BUS 0 C GPIO C CE SPORT2-3 BUS 1 A C PORT A MA A UART0 E M EXTERNAL PORT D D FLASH, SDRAM CONTROL SPORT0-1 16 8M BIT PARALLEL FLASH BOOT ROM (See Table 1)
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide